Figure 5-2: 64-Bit To 32-Bit Core Interface - Xilinx Virtex-4 RocketIO User Manual

Chapter 5: Cyclic Redundancy Check (CRC)
For the different data widths, Data In is always left-aligned within the 64-bit input data
interface. For example, using a 32-bit data width would indicate data is transmitted on a
Data In bit range 63 to 32. See
used Data In bits with their respective RXDATA mapping.
Table 5-3: Examples of Data Rates for CRC Calculation
Notes:
1. Other data rates can be achieved by changing the frequencies of operation and effective data widths.
2. The maximum speed of these configurations is determined by the fabric speed. The maximum speed is
3. The maximum frequency is speed-grade specific.
156
64-bit Input
32-bit
CRC
Calculaton

Figure 5-2: 64-Bit to 32-Bit Core Interface

Data Width CRCINTCLK
64-bit 250 MHz
56-bit 250 MHz
48-bit 250 MHz
40-bit 250 MHz
32-bit 500 MHz
24-bit 500 MHz
16-bit 500 MHz
8-bit 500 MHz
32-bit 250 MHz
24-bit 250 MHz
16-bit 250 MHz
8-bit 250 MHz
typically about 350 MHz.
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Table 5-4 for all combinations of the data width field and
32-bit
&&
(3)
CRCCLK Data Rate
500 MHz
500 MHz
500 MHz
500 MHz
(2)
500 MHz
(2)
500 MHz
(2)
500 MHz
(2)
500 MHz
250 MHz
250 MHz
250 MHz
250 MHz
250 MHz
CRCCLOCKDOUBLE
500 MHz
CRCDATAWIDTH
ug076_ch3_23_090605
(1)
Remarks
16 Gb/s Max rate for CRC
14 Gb/s Max rate at 56-bit
12 Gb/s Max rate at 48-bit
10 Gb/s Max rate at 40-bit
16 Gb/s Max rate for CRC
12 Gb/s Max rate at 24-bit
8 Gb/s Max rate at 16-bit
4 Gb/s Max rate at 8-bit
8 Gb/s
6 Gb/s
4 Gb/s
2 Gb/s
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R