Xilinx Virtex-4 RocketIO User Manual page 15

Schedule of Figures
Section I:
FPGA Level Design
Chapter 1: RocketIO Transceiver Overview
Figure 1-1: RocketIO Multi-Gigabit Transceiver Block Diagram. . . . . . . . . . . . . . . . . . . . 36
Chapter 2: Clocking, Timing, and Resets
Figure 2-1: MGT Column Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-2: High-Speed Dedicated Clocks (GT11CLK_MGT Instance) . . . . . . . . . . . . . . 66
Figure 2-3: REFCLK and GREFCLK Options for an MGT Tile . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-4: MGT Transmit Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2-5: MGT Receive Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 2-6: Transmitter and Receiver Line Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 2-7: PCS Receive Clocking Domains and Datapaths . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 2-8: PCS Transmit Clocking Domains and Datapaths . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 2-9: Low-Latency Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 2-10: DCM Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 2-11 (Cont'd): Receive Clocking Decision Flow (Page 2 of 2). . . . . . . . . . . . . . . . . . 79
Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2). . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 2-12 (Cont'd): Transmit Clocking Decision Flow (Page 2 of 2) . . . . . . . . . . . . . . . . 81
Figure 2-13: External PLL Locked Signal for MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 2-14: Flow Chart of TX Reset Sequence Where TX Buffer Is Used . . . . . . . . . . . . 86
Figure 2-15: Resetting the Transmitter Where TX Buffer Is Used . . . . . . . . . . . . . . . . . . . 87
Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed . . . . . . . . 88
Figure 2-17: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed
and tx_align_err Is Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 2-18: Resetting the Transmitter Where TX Buffer Is Bypassed . . . . . . . . . . . . . . . 93
Figure 2-19: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Used . . . . . . . 94
Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is Used . . 95
Figure 2-21: Resetting the Receiver in Analog CDR Mode Where RX Buffer Is Used . . 96
Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed . . . 97
Figure 2-23: Resetting the Receiver in Analog CDR Mode Where
RX Buffer Is Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 2-24: TXRESET for 8-Byte External Data Interface Width . . . . . . . . . . . . . . . . . . . 100
Chapter 3: PCS Digital Design Considerations
Figure 3-1: Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
www.xilinx.com 15