Xilinx Virtex-4 RocketIO User Manual page 189

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Table 7-6: Bonded Out MGTCLK Sources for XC4VFX20
Table 7-7: Bonded Out MGTCLK Sources for XC4VFX40
Table 7-8: Bonded Out MGTCLK Sources for XC4VFX60
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
LOC Constraint
MGTCLK
GT11CLK_X0Y0 105
GT11CLK_X0Y1 102
GT11CLK_X1Y0
110
GT11CLK_X1Y1 113
LOC Constraint
MGTCLK
GT11CLK_X0Y0 105
GT11CLK_X0Y1 –
GT11CLK_X0Y2
102
GT11CLK_X1Y0 110
GT11CLK_X1Y1 –
GT11CLK_X1Y2 113
LOC Constraint
MGTCLK
GT11CLK_X0Y0 –
GT11CLK_X0Y1 105
GT11CLK_X0Y2 –
GT11CLK_X0Y3 102
GT11CLK_X1Y0
–
GT11CLK_X1Y1 110
GT11CLK_X1Y2 –
GT11CLK_X1Y3 113
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Transceiver Location and Package Pin Relation
XC4VFX20-FF672
CLKN CLKP
AF20 AF21
G26 F26
AF11 AF10
L1 K1
XC4VFX40-FF672
CLKN CLKP
AF20 AF21
– –
G26 F26
AF11 AF10
– –
L1 K1
XC4VFX60-FF672
CLKN CLKP
– –
AF20 AF21
– –
G26 F26
– –
AF11 AF10
– –
L1 K1
XC4VFX40-FF1152
MGTCLK CLKN
105 AP28
– –
102 N34
110 AP4
– –
113 K1
XC4VFX60-FF1152
MGTCLK CLKN
– –
105 AP28
– –
102 N34
– –
110 AP4
– –
113 K1
CLKP
AP29
–
M34
AP3
–
J1
CLKP
–
AP29
–
M34
–
AP3
–
J1
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