Xilinx Virtex-4 RocketIO User Manual page 301

R
Table C-9: Dynamic Reconfiguration Port Memory Map: MGTA Address 63–67
Bit
63 Def
15
14
CLK_COR_SEQ_2_2
13
[4:0]
12
11
10
9
8
N/A
7
6
CLK_COR_SEQ_2_1
5
[10:0]
4
3
2
1
0
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
64 Def
CLK_COR_SEQ_1_2
[4:0]
RESERVED
N/A
[15:0]
CLK_COR_SEQ_1_1
[10:0]
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Address
65 Def 66
0
0
CHAN_BOND_SEQ_2_2
0
[4:0]
0
0
0
0
0
0
0
CHAN_BOND_SEQ_2_1
0
[11:0]
0
0
0
0
0
Memory Map
Def 67
CHAN_BOND_SEQ_1_2
[4:0]
N/A
CHAN_BOND_SEQ_1_1
[11:0]
Def
N/A
301