Example Of A Reduced-Latency System; Xaui; System Characteristics - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design

Example of a Reduced-Latency System

XAUI

System Characteristics

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TX
Since this is a channel-bonded system, so minimizing channel-to-channel skew is a
concern. To provide the lowest possible skew, GREFCLK should be used as the
synchronization clock.
Based on the encoding, this would lead the user to pick Use Model TX_2B or TX_2F. The
system summarized in
to
(Refer to
Table 8-13: Latency for Use Model TX_2B or TX_2F
Notes:
1. T
2. T
3. 1 UI = 1/3.125e9 = 320 ps
4. 64B/66B encoding/decoding is not supported.
The system summarized in
standard does support channel bonding and can tolerate fairly significant skew, Use Model
TX_3A would be a good choice.
The worst-case skew
according to
230
3.125 Gb/s Data Rate
156.25 MHz Reference Clock
4-Lane Channel-Bonded System
40-bit Internal Data Width
2-byte Fabric Width
8B/10B Encoding
Clock Correction Supported
(Reference of link partner can be ±100 ppm from nominal 156.25 MHz)
Table 8-13
Table 8-10, page 218: ~2.53 UI (~810 ps). The latency through this system is 168.96 ns.
Table 8-1, page 194
Transmit Blocks
Fabric Interface (2 Byte)
Encoding (8B/10B)
TX Buffer
(4)
64B/66B Format (Bypass)
PMA Interface
PMA Register
PISO
Total:
= T = T
PMA TXCLK0 PCS TXCLK
= 1/156.25 MHz = 6.4 ns
TXUSRCLK2
(Table
Table 8-1 and
www.xilinx.com
incurs the smallest possible worst-case skew according
and Figure 8-5, page 203.)
Latency
2 TXUSRCLK2 + 1 TXUSRCLK
3 TXUSRCLK
3 + 1/2 TXUSRCLK / PCS TXCLK
1 PCS TXCLK
1 PCS TXCLK
1 PMA TXCLK0
68 UI
= 1 / 156.25MHz
TXUSRCLK
Table 8-14 incurs quite a significant penalty in latency. Since the
8-10) increases to ~23.5313 UI (~7.53 ns). The latency, however,
Figure 8-13, page 212, reduces to 85.76 ns, a significant savings.
Latency (ns)
* 2 = 12.8 ns
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
25.60
38.40
44.80
12.80
12.80
12.80
21.76
168.96