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Xilinx Virtex-4 User Manual

Xilinx Virtex-4 User Manual

Fpga embedded tri-mode ethernet mac
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Virtex-4 FPGA
Embedded Tri-Mode
Ethernet MAC
User Guide
UG074 (v2.2) February 22, 2010
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  • Page 1 Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010 www.BDTIC.com/XILINX...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.
  • Page 3 Revision History The following table shows the revision history for this document. Date Version Revision 11/11/04 Initial Xilinx release. 07/05/05 In Chapter 2: • Revised Table 2-6, page “Tie-Off Pins,” page 24, and Table 2-10, page In Chapter 3: • Revised...
  • Page 4 “Client Side Data Width,” page 157 options. • Replaced “File Generation” with new content. • Replaced Figure 5-1, page 153. 02/09/06 1.4.1 Cleaned up formatting issues. No content changes. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 5 Chapter 4 incorporated into section “8-Bit Data Client.” • Table 4-3: Consolidated “RISING” and “FALLING” RGMII signals into single signals with revised descriptions. Added Note (1) to RGMII_TX_CTL_# and RGMII_RX_CTL_#. www.BDTIC.com/XILINX UG074 (v2.2) February 22, 2010 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 6 SmartModel with references to SecureIP throughout this section. Added “SecureIP Model,” page 155. • Chapter 7: Removed content discussing Ethernet MAC wrappers and replaced it with“Using the Embedded Ethernet MAC,” page 167. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 7 • Updated description of Link Status and added table note to Table 4-11, page 141. • Appendix A: Changed T to Clock Low and T to Clock High in Figure A-1, xMACWL xMACWH page 171. www.BDTIC.com/XILINX UG074 (v2.2) February 22, 2010 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 8 Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 9: Table Of Contents

    ............. 93 www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 10 ......... . . 157 www.BDTIC.com/XILINX www.xilinx.com...
  • Page 11 Timing Diagram and Timing Parameter Tables ......171 www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 12 Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 13: Preface: About This Guide

    This document is the Virtex®-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide. Guide Contents This user guide contains the following chapters: • Chapter 1, “Introduction,” introduces the Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC and summarizes its features. • Chapter 2, “Ethernet MAC Architecture,” describes the architecture of the Ethernet MAC and defines its signals.

  • Page 14: Conventions

    The typographical conventions in the following table are used in this document: Convention Meaning or Use Example See the Virtex-4 Data Sheet References to other manuals more information. Italic font If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol, the two nets are not connected.

  • Page 15: Chapter 1: Introduction

    UG074_1_01_012408 Figure 1-1: Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC The Virtex-4 FPGA Ethernet MAC has two Ethernet MACs sharing a single host interface. Either or both of the Ethernet MACs can be selected to access the Ethernet MAC registers. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...

  • Page 16: Features

    Chapter 1: Introduction Features The key features of the Virtex-4 FPGA Ethernet MAC are: • Fully integrated 10/100/1000 Mb/s Ethernet MAC • Designed to the IEEE Std 802.3-2002 specification • Configurable full-duplex operation in 10/100/1000 Mb/s • Configurable half-duplex operation in 10/100 Mb/s •...

  • Page 17: Chapter 2: Ethernet Mac Architecture

    “Ethernet MAC Signal Descriptions” Architecture Overview The Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC supports 10/100/1000 Mb/s data rates and is designed to IEEE Std 802.3-2002 specifications. The Ethernet MAC can operate as a single speed Ethernet MAC at 10, 100, or 1000 Mb/s or as a tri-mode Ethernet MAC.
  • Page 18 Ethernet MAC (10 Mb/s, 100 Mb/s, or 1000 Mb/s) and the Ethernet MAC mode settings (GMII, MII, RGMII, SGMII, and 1000BASE-X). www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 19 Host Bus MDIO Interface Host to External PHY MDIO Interface Interface DCR Bus Configuration Registers Statistics tx_stats_vec rx_stats_vec UG074_2_02_081308 Figure 2-2: Functional Block Diagram of 10/100/1000 Ethernet MAC www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 20: Ethernet Mac Primitive

    Chapter 2: Ethernet MAC Architecture Ethernet MAC Primitive The Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC has an EMAC primitive. The primitive contains access to both Ethernet MACs (EMAC0 and EMAC1). By using the Ethernet MAC primitive, any of these supported interfaces can be created: •...
  • Page 21 HOSTWRDATA[31:0] EMAC#CLIENTANINTERRUPT HOSTEMAC1SEL EMAC#PHYTXCHARDISPMODE DCREMACENABLE EMAC#PHYTXCHARDISPVAL EMACDCRACK EMAC#PHYTXCHARISK EMACDCRDBUS[0:31] PHYEMAC#TXBUFERR DCREMACABUS[8:9] EMAC#PHYMCLKOUT DCREMACCLK PHYEMAC#MCLKIN DCREMACDBUS[0:31] PHYEMAC#MDIN DCREMACREAD EMAC#PHYMDOUT DCREMACWRITE EMAC#PHYMDTRI DCRHOSTDONEIR ug074_2_03_101804 Figure 2-3: Ethernet MAC Primitive www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 22: Ethernet Mac Signal Descriptions

    Configurable inter-frame gap (IFG) adjustment for full-duplex CLIENTEMAC#TXIFGDELAY[7:0] Input mode. Asserted by the client to force the Ethernet MAC to corrupt the CLIENTEMAC#TXUNDERRUN Input current frame. CLIENTEMAC#TXCLIENTCLKIN Input “Transmit Clocking Scheme” in Chapter www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 23 This signal is asserted to notify the client that an incoming receive frames destination address does not match any addresses in the EMAC#CLIENTRXFRAMEDROP Output address filter. The signal functions even when the address filter is not enabled. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 24 Input Asserted by client to transmit a pause frame. The amount of pause time for the transmitter as defined in the CLIENTEMAC#PAUSEVAL[15:0] Input IEEE Std 802.3-2002 specification. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 25: Clock Signals

    Notes: 1. The Ethernet MAC uses this clock to generate an internal clock that eliminates clock skew between the Ethernet MAC and the client logic in the FPGA. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 26: Host Interface Signals

    2. When using the PowerPC 405 processor as a host processor and using the DCR bus for host access, the host bus signals are used to read the optional FPGA fabric-based statistics registers. See “Interfacing to an FPGA Fabric-Based Statistics Block” in Chapter www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...

  • Page 27: Reset And Clientemac#Dcmlocked Signals

    If a DCM is not used, both CLIENTEMAC#DCMLOCKED ports from EMAC0 and EMAC1 must be tied High. If any Ethernet MAC is not used, CLIENTEMAC#DCMLOCKED must be tied to High. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 28: Tie-Off Pins

    Configuration Vectors This section describes the 80 tie-off pins (TIEEMAC#CONFIGVEC[79:0]) used to configure the Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC. The values of these tie-off pins are loaded into the Ethernet MAC at power-up or when the Ethernet MAC is reset.
  • Page 29 Receive 16-bit client interface enable. When asserted, the RX TIEEMAC#CONFIGVEC[65] Input client data interface is 16 bits wide. When deasserted, the RX client data interface is 8 bits wide. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 30 CLIENTEMAC#TXIFGDELAY[7:0] port TIEEMAC#CONFIGVEC[54] Input and sets the IFG accordingly. When this bit is 0, the transmitter always inserts at least the legal minimum IFG. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 31 Ethernet MAC address of AA-BB-CC-DD-EE-FF is stored in byte [47:0] as 0xFFEEDDCCBBAA. Tied to the same Ethernet MAC address as TIEEMAC#UNICASTADDR[47:0]. Notes: 1. A reset is needed before changes on TIEEMAC#CONFIGVEC[73] and [70:64] take effect. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 32: Management Data Input/Output (Mdio) Interface Signals

    Chapter 2: Ethernet MAC Architecture Unicast Address Table 2-12 describes the 48 tie-off pins (TIEEMAC#UNICASTADDR[47:0]) used to set the Ethernet MAC address for the Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC. Table 2-12: Unicast Address Pins Signal Direction Description This 48-bit wide tie-off is used to set the Ethernet MAC unicast address used by the address filter block to see if the incoming frame is destined for the Ethernet MAC.
  • Page 33 16 bits wide, this signal is the clock input port used in for the CLIENTEMAC#RXCLIENTCLKIN/2. 1000BASE-X “Receive (RX) Client – 16-bit Wide Interface” PCS/PMA in Chapter www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 34: Rocketio Multi-Gigabit Transceiver Signals

    RocketIO Multi-Gigabit Transceiver Signals Table 2-15 shows the signals used to connect the Ethernet MAC to the RocketIO Multi- Gigabit Transceiver (see UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide). Table 2-15: Multi-Gigabit Transceiver Connections Signal Direction...
  • Page 35 Clause 36. If asserted High, the optical receiver has detected light. PHYEMAC#SIGNALDET Input If deasserted Low, indicates the absence of light. If unused, this signal should be tied High for correct operation. EMAC#CLIENTANINTERRUPT Output Interrupt upon auto-negotiation. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 36 Chapter 2: Ethernet MAC Architecture www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 37: Client Interface

    Figure 3-1 shows a block diagram of the transmit client interface. In 16-bit client mode, PHYEMAC#MIITXCLK functions as CLIENTEMAC#TXCLIENTCLKIN/2. TIEEMAC#CONFIGVEC[66] selects between an 8-bit or 16-bit client interface. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 38 CLIENTEMAC#TXUNDERRUN (Internal Signal) TX_UNDERRUN CLIENTEMAC#TXFIRSTBYTE (Internal Signal) TIEEMAC#CONFIGVEC[66] TXFIRSTBYTEREG (Internal Signal) TX_IFG_DELAY[7:0] CLIENTEMAC#TXIFGDELAY[7:0] (Internal Signal) FPGA Fabric Ethernet MAC Block ug074_3_03_070105 Figure 3-1: Transmit Client Block Diagram www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 39 /I2/ IDLE_2 (K28.5/D16.2) 2 bytes Carrier Extend (K23.7) 1 byte Start of Packet (K27.7) 1 byte End of Packet (K29.7) 1 byte Error Propagation (K30.7) 1 byte www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 40: Transmit (Tx) Client - 8-Bit Wide Interface

    /T/ /R/ (SGMII or 1000BASE-X PCS/PMA only) EMAC#PHYTXCHARISK (SGMII or 1000BASE-X PCS/PMA only) EMAC#PHYTXCHARDISPMODE (SGMII or 1000BASE-X PCS/PMA only) ug074_3_05_080705 Figure 3-3: Normal Frame Transmission Across Client Interface www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 41 /T/ /R/ (SGMII or 1000BASE-X PCS/PMA only) EMAC#PHYTXCHARISK (SGMII or 1000BASE-X PCS/PMA only) EMAC#PHYCHARDISPMODE (SGMII or 1000BASE-X PCS/PMA only) ug074_3_06_072705 Figure 3-4: Frame Transmission with Client-Supplied FCS www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 42 /T/ /R/ /I1/ (SGMII or 1000BASE-X PCS/PMA only) EMAC#PHYTXCHARISK (SGMII or 1000BASE-X PCS/PMA only) EMAC#PHYCHARDISPMODE (SGMII or 1000BASE-X PCS/PMA only) ug074_3_07_072705 Figure 3-5: Frame Transmission with Underrun www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 43 The Ethernet MAC defers the assertion of EMAC#CLIENTTXACK to comply with inter-packet gap requirements and flow control requests. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 44 For more information on enabling and disabling jumbo frame handling, see “Configuration Registers,” page www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 45 EMAC#CLIENTTXCOLLISION signal to meet Ethernet timing requirements. This operation is shown in Figure 3-8. CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#TXD[7:0] CLIENTEMAC#TXDVLD 8 Clocks Maximum EMAC#CLIENTTXACK CLIENTEMAC#TXFIRSTBYTE CLIENTEMAC#TXUNDERRUN EMAC#CLIENTTXCOLLISION EMAC#CLIENTTXRETRANSMIT ug074_3_10_101004 Figure 3-8: Collision Handling - Frame Retransmission Required www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 46 In full-duplex configurations, the minimum IFG is 12 bytes (96 bit times). In half-duplex configurations, the minimum supported IFG is 18 bytes (144 bit times) when using the MII physical interface, or 26 bytes (208 bit times) when using the RGMII physical interface. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...

  • Page 47: Transmit (Tx) Client - 16-Bit Wide Interface

    EMAC#PHYTXCHARDISPMODE, the MGT encodes the incoming data to the appropriate 8B/10B stream. Figure 3-11 shows the timing of a normal outbound frame transfer for the case with an even number of bytes in the frame. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 48 Figure 3-11: 16-Bit Transmit (Even Byte Case) Figure 3-12 shows the timing of a normal outbound frame transfer for the case with an odd number of bytes in the frame. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 49 CLIENTEMAC#TXD[15:0]. In 16-bit mode, this one PHYEMAC#MIITXCLK clock cycle IFG corresponds to a 2-byte gap (versus a 1-byte gap in 8-bit mode) between frames in the back-to-back transfer. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 50 DA1, DA0 DA3, DA2 DA5, DA4 CLIENTEMAC#TXDVLD CLIENTEMAC#TXDVLDMSW EMAC#CLIENTTXACK CLIENTEMAC#TXFIRSTBYTE CLIENTEMAC#TXUNDERRUN EMAC#CLIENTTXCOLLISION EMAC#CLIENTTXRETRANSMIT 1st Frame 2nd Frame ug074_3_16_101004 Figure 3-14: 16-Bit Transmit Back-to-Back Transfer (Odd Byte Case) www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 51: Receive (Rx) Client - 8-Bit Wide Interface

    This is after receipt of the FCS field (and after reception of the carrier extension if present). Therefore, either EMAC#CLIENTRXGOODFRAME or EMAC#CLIENTRXBADFRAME is asserted following frame reception at the beginning of the IFG. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 52 Figure 3-16: Inbound Frame Transfer (Front) CLIENTEMAC#RXCLIENTCLKIN PHYEMAC#RXCHARISCOMMA PHYEMAC#RXCHARISK /I1/ DATA PHYEMAC#RXD[7:0] EMAC#CLIENTRXD[7:0] PREAMBLE Data EMAC#RXCLIENTDVLD EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXBADFRAME EMAC#CLIENTRXSTATS[6:0] EMAC#CLIENTRXSTATSVLD UG074_3_19_072705 Figure 3-17: Inbound Frame Transfer (Back) www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 53 Figure 3-19: Unsuccessful Frame Reception (SGMII and 1000BASE-X PCS/PMA Modes) The following conditions cause the assertion of EMAC#CLIENTRXBADFRAME: • Standard Conditions: • FCS errors occur. • Packets are shorter than 64 bytes (undersize or fragment frames). www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 54 Even though the FCS is passed up to the client, it is also verified by the Ethernet MAC, and EMAC#CLIENTRXBADFRAME is asserted if the FCS check fails. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 55 For more information on enabling and disabling jumbo frame handling, see “Configuration Registers,” page www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 56: Receive (Rx) Client - 16-Bit Wide Interface

    The PHYEMAC#RXCLK is used as the input clock port for the CLIENTEMAC#RXCLIENTCLKOUT divided by two, as shown in the receive client block diagram in Figure 3-2, page 39. Using a DCM with the receive client clock, www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 57 3-23), EMAC#CLIENTRXDVLDMSW is deasserted one clock cycle earlier compared to the EMAC#CLIENTRXDVLD signal, after the reception of the frame. EMAC#CLIENTRXD[7:0] contains the data in this odd byte case. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 58: Address Filtering

    Table 3-3: EMAC#CLIENTRXDVLD and EMAC#CLIENTRXFRAMEDROP Values When AF is Disabled EMAC#CLIENTRXDVLD EMAC#CLIENTRXFRAMEDROP Result of an Incoming RX Frame No incoming RX frame AF passes RX frame AF rejects RX frame www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 59 CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXDVLD EMAC#CLIENTRXD[7:0] EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXFRAMEDROP Previous Frame Current Frame Dropped Passed ug074_3_26_080805 Figure 3-24: Frame Matching Timing Diagram (8-Bit Mode) www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 60 CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXDVLD EMAC#CLIENTRXD[7:0] EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXFRAMEDROP Previous Frame Current Frame Passed Dropped ug074_3_28_080805 Figure 3-26: Frame Matching Failed Timing Diagram (8-Bit Mode) www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 61: Flow Control Block

    The left Ethernet MAC is illustrated as performing a loopback implementation; this results in the FIFO filling up over time. Without flow control, this FIFO eventually fills and overflows, resulting in the corruption or loss of Ethernet frames. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 62 MAC ceases transmission before the client FIFO of the left Ethernet MAC is overflowed. This provides time to empty the FIFO to a safe level before normal operation resumes. It also safe guards the system against FIFO overflow conditions and frame loss. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 63 If any match is false or the Ethernet MAC flow control logic for the receiver is disabled, the frame is ignored by the flow control logic and passed up to the client. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 64 Ethernet MAC immediately resumes transmission (i.e., there is no wait for the original requested pause duration to expire). This PAUSE control frame can, therefore, be considered a “pause cancel” command. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...

  • Page 65: Statistics Vector

    TX_STATISTICS_VECTOR contains the statistics for the frame transmitted. The vector is driven synchronously by the transmitter clock, CLIENTEMAC#TXCLIENTCLKIN, following frame transmission. The bit field definition for the transmitter statistics vector is defined in Table 3-4. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 66 EMAC#CLIENTTXSTATSVLD is asserted as illustrated in Figure 3-34. EMAC#CLIENTTXSTATSBYTEVLD is asserted if an Ethernet MAC frame byte (DA to FCS inclusive) is being transmitted. The signal is valid on every CLIENTEMAC#TXCLIENTCLKIN cycle. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 67 Asserted if the previous frame was deferred for an excessive amount of time as defined by the EXCESSIVE_DEFERRAL maxDeferTime constant in the IEEE Std 802.3- 2002 specification. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 68 This vector is muxed out to a seven-bit wide signal EMAC#CLIENTRXSTATS[6:0] as shown in Figure 3-35. CLIENTEMAC#RXCLIENTCLKIN RX_STATISTICS_VALID (internal signal) RX_STATISTICS_VECTOR[26:0] (internal signal) EMAC#CLIENTRXSTATSVLD EMAC#CLIENTRXSTATS[6:0] [6:0] [13:7] [20:14] [26:21] ug074_3_37_080805 Figure 3-35: Receiver Statistics MUX Timing www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 69 Ethernet MAC Block FPGA Fabric EMAC#CLIENTRXSTATSBYTEVLD EMAC#CLIENTRXSTATS[6:0] EMAC#CLIENTRXSTATSVLD CLIENTEMAC#RXCLIENTCLKIN RXSTATSDEMUX RESET RXSTATSVEC[26:0] RXSTATSVLD User Defined CLIENTEMAC#RXCLIENTCLKIN Statistics Processing Block ug074_3_38_080805 Figure 3-36: Receiver Statistics MUX Block Diagram www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 70 Asserted if the previous frame is error free, contains the special control frame identifier in the LT field, but BAD_OPCODE contains an OPCODE unsupported by the Ethernet MAC (any OPCODE other than PAUSE). www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 71 A custom statistics counter can be implemented in the FPGA fabric to collect the statistics. A parameterizable Ethernet statistics core is available from the LogiCORE™ libraries. For more information, see: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PR ODUCTS&sSecondaryNavPick=Intellectual+Property&key=ETHERNET_STATS When the PowerPC 405 processor is used as a host processor, it can access the statistics counter registers in the FPGA fabric through the DCR bridge in the host interface.

  • Page 72: Host Interface

    Generic Host Bus Virtex- 4 FPGA DCRHOSTDONEIR Bridge DCR Bus PPC405 EMAC1 DCREMACENABLE Host Interface EMAC1 EMAC0 Ethernet MAC Block Processor Block ug074_3_40_080805 Figure 3-38: Host Interface www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 73 DCR. Access to the management interface depends on the type of transaction. Table 3-6 shows the access method required for each transaction type. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 74: Host Clock Frequency

    MDIO access Host Clock Frequency The host clock (HOSTCLK) is used to derive the MDIO clock, MDC, and is subject to the same frequency restrictions. See the Virtex-4 FPGA Data Sheet for the HOSTCLK frequency parameters. Configuration Registers The Ethernet MAC has seven configuration registers. These registers are accessed through the host interface and can be written to at any time.
  • Page 75 Reset: When this bit is 1, the receiver is reset. The bit [31] automatically reverts to 0, This reset also sets all of the receiver TIEEMAC#CONFIGVEC[53] configuration registers to their default values. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 76 CLIENTEMAC#PAUSEREQ signal is asserted and a flow [30] TIEEMAC#CONFIGVEC[61] control frame is sent from the transmitter. When this bit is 0, the CLIENTEMAC#PAUSEREQ signal has no effect. [31] Reserved. – www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 77 Speed selection: The speed of the Ethernet MAC is defined by the following values: 10 = 1000 Mb/s [31:30] TIEEMAC#CONFIGVEC[72:71] 01 = 100 Mb/s 00 = 10 Mb/s 11 = N/A www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 78 134. This 2-bit vector is defined with the following values: [31:30] All 0s 10 = 1000 Mb/s 01 = 100 Mb/s 00 = 10 Mb/s 11 = N/A www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 79 Low write-enable signal. The lower HOSTOPCODE bit (bit[0]) is a “don’t care.” HOSTCLK HOSTMIIMSEL HOSTOPCODE[1] HOSTADDR[8:0] HOSTADDR[9] HOSTWRDATA[31:0] ug074_3_42_080805 Figure 3-40: Configuration Register Write Timing www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 80: Address Filter Registers

    Unicast Address (Word 0) 0x380 Unicast Address (Word 1) 0x384 Multicast Address Table Access (Word 0) 0x388 Multicast Address Table Access (Word 1) 0x38C Address Filter Mode 0x390 www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 81 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED UNICAST_ADDRESS[47:32] 0x384 Description Default Value [15:0] Unicast Address [47:32]. TIEEMAC#UNICASTADDR[47:32] [31:16] Reserved. – www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 82 A timing diagram for writing to the Address Filter Registers is the same as the one shown for writing to the Ethernet MAC Configuration Registers (Figure 3-40). www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 83: Using The Dcr Bus As The Host Bus

    Alternatively, the host interface can also provide an interrupt request to inform the host of access completion. The user can select either the polling or the interrupt method to inform the host of access status. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 84 Data – Data input from the DCR bus for the Ethernet MAC registers is written into this [0:31] register, and the least significant word of data is read out from the Ethernet MAC registers Undefined and deposited into this register. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 85 Address Code – the DCR bus bridge translates this address code into the Ethernet MAC [22:31] All 0s register address. See Table 3-30, page 91 for address code. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 86 The MIIMWRDATA register temporarily holds MDIO write data for output to the MDIO write data bus. In the case of an MDIO read, there is no need to www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 87 EMAC0 [31] Statistics IP Read Interrupt Request bit. EMAC0 Notes: 1. For more information on Statistics IP, see “Interfacing to an FPGA Fabric-Based Statistics Block” in Chapter www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 88 Data- temporarily holds MDIO write data for output onto the host write data bus. undefined Notes: 1. See “Interfacing to an FPGA Fabric-Based Statistics Block” in Chapter www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 89: Description Of Ethernet Mac Register Access Through The Dcr Bus

    OPCODE#[1:0] (see Figure 3-39, page 73). Data in the dataRegLSW is output on the WRD#[31:0]. These signals are output to EMAC0 or EMAC1 when selected by the www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 90 DCR RDYstatus register is provided to indicate when a multiple-cycle access is ready. This register is allows the host to use the polling method for accesses requiring only a few multiple host clock cycles. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...

  • Page 91: Address Code

    Address codes for statistics IP registers and Ethernet MAC Configuration registers match the 1G Ethernet MAC Host Bus address as specified in the Xilinx® 1G Ethernet MAC core at: http://www.xilinx.com/support/documentation/ip_documentation/gig_eth_mac_ds200.pdf Table 3-29: Address Code Groups for DCR Host Bus Access...
  • Page 92 0x7A0 0x7A0 IRENABLE Interrupt request enable. 0x7A4 0x7A4 Reserved. 0x7A8:0x7AF MIIMWRDATA MDIO write data. 0x7B0 0x7B0 Decode address for MDIO MIIMCNTL 0x7B4 0x7B4 address output. Reserved. 0x7B8:0x7FF www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 93: Mdio Interface

    The two different MDIO transaction types for writes and reads are described in “Write Transaction,” “Read Transaction.” These abbreviations are used in this chapter: Operation code PHYAD PHY address Preamble REGAD Register address Start of frame Turnaround www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 94 MMDs such as a reset or power- down command. This requirement dictates that the PHYAD for any particular MMD must not be set to 0 to avoid possible MDIO contention. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 95: Mdio Implementation In The Emac

    TIEEMAC#CONFIGVEC[78:74]). However, it is still internally connected to the MDIO and replies to a read or write transaction, if addressed. The PHYAD of the PCS/PMA sublayer must not be addressed. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 96 MMD (for example, an external PHY device) by providing the connections illustrated in Figure 3-49. Externally connected MMDs (MDIO slaves) must have different non-zero physical addresses (PHYAD) from the non-zero address of the PCS/PMA sublayer. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 97: Accessing Mdio Via The Emac Host Interface

    PCS/PMA layer by providing PHYEMAC#MCLKIN and tying TIEEMAC#CONFIGVEC[73] High. Access to the MDIO interface through the management interface is shown in the Figure 3-52 timing diagram. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 98 Figure 3-52: MDIO Access Through the Management Interface For register map details of the physical layer devices and a complete description of the operation of the MDIO interface itself, see IEEE specification 802.3-2002. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...

  • Page 99: Chapter 4: Physical Interface

    The wrapper for the different physical interfaces are provided in the Xilinx® CORE Generator™ tool. The interfaces are available in both VHDL and Verilog. The wrapper files created by the CORE Generator tool will contain the clocking logic.
  • Page 100 HOSTADDR[9:0] HOSTCLK HOSTMIIMSEL HOSTOPCODE[1:0] HOSTREQ HOSTMIIMRDY HOSTRDDATA[31:0] HOSTWRDATA[31:0] HOSTEMAC1SEL DCREMACENABLE EMACDCRACK EMACDCRDBUS[0:31] DCREMACABUS[8:9] DCREMACCLK DCREMACDBUS[0:31] DCREMACREAD DCREMACWRITE DCRHOSTDONEIR UG074_3_50_022007 Figure 4-1: Ethernet MAC Configured in MII Mode www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 101: Mii Clock Management

    MII_RXD_#[3:0] CLIENTEMAC#DCMLOCKED IBUF Note 1: A regional buffer (BUFR) can replace this BUFG. Refer to the Virtex-4 User Guide for BUFR usage guidelines. UG074_3_51_032207 Figure 4-2: MII Clock Management MII Clock Management with Clock Enable It is possible to only use two BUFGs. To accomplish this BUFG reduction, the client and MII logic must be constrained to run at 125 MHz.
  • Page 102 (clocked on the falling edge of the MII clock) and routed to the client clock inputs. The client logic must also be clock enabled to achieve the correct www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 103 MII clock (and clock enabled like the rest of the client logic), the data removal problem will not happen. Figure 4-5 illustrates the timing diagram. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 104: Mii Signals

    Recovered clock from data stream by PHY MII_RXD[3:0]_# Input Receive data from PHY MII_RX_DV_# Input Receive data valid control signal from PHY MII_RX_ER_# Input Receive data error signal from PHY www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 105: Gigabit Media Independent Interface (Gmii) Signals

    GMII Interface Figure 4-6 shows the Ethernet MAC configured with GMII as the physical interface. In this interface, not all the ports of the Ethernet MAC are used. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 106 HOSTCLK GMII_TX_ER_# HOSTMIIMSEL HOSTOPCODE[1:0] HOSTREQ HOSTMIIMRDY HOSTRDDATA[31:0] HOSTWRDATA[31:0] HOSTEMAC1SEL DCREMACENABLE EMACDCRACK EMACDCRDBUS[0:31] DCREMACABUS[8:9] DCREMACCLK DCREMACDBUS[0:31] DCREMACREAD DCREMACWRITE DCRHOSTDONEIR ug074_3_52_032207 Figure 4-6: Ethernet MAC Configured in GMII Mode www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 107: Gmii Clock Management

    GMII clock with respect to the data, in order to sample a 2 ns setup, 0 ns hold window at the device pads. Phase shifting is applied to the DCM to fine tune the setup and www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 108 LOGIC IBUF CLIENTEMAC1RXCLIENTCLKIN GMII_RXD_#[7:0] EMAC1CLIENTRXCLIENTCLKOUT BUFG PHYEMAC1RXD[7:0] IBUFG CLK0 CLIENTEMAC1DCMLOCKED GMII_RX_CLK_# CLKIN PHYEMAC1RXCLK CLKFB UG074_3_54_040609 Figure 4-8: 1 Gb/s GMII Clock Management with Two Ethernet MACs Enabled www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 109 PHY. Since GMII_TX_CLK_# is derived from EMAC#CLIENTTXGMIIMIICLKOUT or MII_TX_CLK_#, its frequency automatically changes between 125 MHz, 25 MHz, or 2.5 MHz depending on the speed setting of the Ethernet MAC. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 110: Tri-Mode Operation With Byte Phy Enabled (Full-Duplex Only)

    At 1 Gb/s all external logic is clocked at 125 MHz. At 100 Mb/s and 10 Mb/s, the logic is clocked at 12.5 MHz and 1.25 MHz, respectively. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 111 Logic EMAC#CLIENTRXCLIENTCLKOUT IBUF IDDR PHYEMAC#RXD[7:4] GMII_RXD_#[7:4] SPEED_IS_10_100 CLIENTEMAC#DCMLOCKED IBUFG rx_clk_div2 CLK0 PHYEMAC#RXCLK CLKIN GMII_RX_CLK_# BUFGMUX CLKFB UG074_3_77_031009 Figure 4-10: Tri-Mode GMII Clock Management with Byte PHY Enabled www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 112: Gmii Signals

    2.5 MHz when operating at 10 Mb/s and 2.5 MHz is below the DCM low frequency threshold for Virtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds, input setup and hold margins increase appropriately and the input MII data can be sampled correctly without use of the DCM.

  • Page 113: 10/100/1000 Rgmii

    1 Gb/s RGMII Interface Figure 4-11 shows the Ethernet MAC configured with RGMII as the physical interface. In this interface, not all the ports of the Ethernet MAC are used. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 114 HOSTADDR[9:0] HOSTCLK HOSTMIIMSEL HOSTOPCODE[1:0] HOSTREQ HOSTMIIMRDY HOSTRDDATA[31:0] HOSTWRDATA[31:0] HOSTEMAC1SEL DCREMACENABLE EMACDCRACK EMACDCRDBUS[0:31] DCREMACABUS[8:9] DCREMACCLK DCREMACDBUS[0:31] DCREMACREAD DCREMACWRITE DCRHOSTDONEIR UG074_3_56_032207 Figure 4-11: Ethernet MAC Configured in RGMII Mode www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 115: Gb/S Rgmii Clock Management

    LOGIC PHYEMAC#MIITXCLK CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXCLIENTCLKOUT IBUF PHYEMAC#RXD[3:0] RGMII_RXD_#[3:0] BUFG IBUFG PHYEMAC#RXD[7:4] CLK0 RGMII_RXC_# CLKIN PHYEMAC#RXCLK CLKFB CLIENTEMAC#DCMLOCKED UG074_3_57_031009 Figure 4-12: 1 Gb/s RGMII Hewlett Packard v1.3 Clock Management www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 116 CLKFB CLIENTEMAC#DCMLOCKED Notes: 1) An optional IDELAY can be used to adjust setup and hold timing. UG074_58_040609 Figure 4-13: 1 Gb/s RGMII Hewlett Packard v2.0 Clock Management www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 117: Tri-Mode Rgmii V2.0

    10 Mb/s and 2.5 MHz is below the DCM low frequency threshold for Virtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds, input setup and hold margins increase appropriately and the input RGMII data can be sampled correctly without use of the DCM.
  • Page 118 Notes: CLKFB 1) A regional buffer (BUFR) can replace this BUFG. Refer to the Virtex-4 User Guide for BUFR usage guidelines. UG074_3_78_031009 Figure 4-14: Tri-Mode RGMII v2.0 Clock Management An IDELAY is used to generate 2 ns of skew required between RGMII_TXC_# and RGMII_TXD_# at the pin level.
  • Page 119 Notes: CLKFB 1) A regional buffer (BUFR) can replace this BUFG. Refer to the Virtex-4 User Guide for BUFR usage guidelines. UG074_3_79_031009 Figure 4-15: Alternative Tri-Mode RGMII v2.0 Clock Management The CLIENTEMAC#DCMLOCKED port must be tied HIGH. The RGMII_RXC_# is generated from the PHY and connected to the PHYEMAC#RXCLK pin and receive logic through a DCM and a BUFG.

  • Page 120: Tri-Mode Rgmii V1.3

    10 Mb/s and 2.5 MHz is below the DCM low frequency threshold for Virtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds, input setup and hold margins increase appropriately and the input RGMII data can be sampled correctly without use of the DCM.
  • Page 121 CLKIN BUFGMUX RGMII_RXC_# Notes: CLKFB 1) A regional buffer (BUFR) can replace this BUFG. Refer to the Virtex-4 User Guide for BUFR usage guidelines. UG074_3_67_031009 Figure 4-16: Tri-Mode RGMII v1.3 Clock Management www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...

  • Page 122: Rgmii Signals

    This signal is RXDV on the rising edge of RGMII_RXC_#, and an RGMII_RX_CTL_# Input encoded RXERR on the falling edge. Notes: 1. See the Hewlett Packard RGMII specification v1.3 or v2.0 (section 3.4) for more information. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 123: 10/100/1000 Serial Gigabit Media Independent Interface (Sgmii)

    10 Mb/s operation (see “The FPGA RX Elastic Buffer Requirement”). However, in logical implementations where this case is proven reliable, this option is preferred because of its lower logic utilization. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 124 Following frame reception in the interframe gap period, idles are removed from the received datastream to return the RX elastic buffer to half-full occupancy. This task is performed by the clock correction circuitry (see UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide).
  • Page 125 Additionally, the underflow and overflow thresholds are not exact. Figure 4-18 illustrates the elastic buffer depths and thresholds of MGTs in Virtex-4 devices. Each FIFO word corresponds to a single character of data (equivalent to a single byte of data following 8B/10B decoding).
  • Page 126 Since there is a worst-case scenario of one clock edge difference every 5000 clock periods, the maximum number of clock cycles (bytes) that can exist in a single frame passing through the buffer before an error occurs is 5000 x 56 = 280000 bytes. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 127 FPGA Ethernet MAC 10BASE-T TXP/TXN 100BASE-T 1000BASE-T Twisted Copper Pair Elastic RXP/RXN Buffer 125 MHz - 100 ppm UG074_3_82_012408 Figure 4-20: SGMII Implementation Using Shared Clock Sources www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 128 Figure 4-21: SGMII Implementation Using a Logic Buffer Using the SGMII in this configuration eliminates the possibility of buffer error if the clocks are not tightly controlled enough to use the MGT elastic buffer. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 129 SGMII or 1000BASE-X PCS/PMA. By using the CORE Generator tool, the time required to instantiate the Ethernet MAC into a usable design is greatly reduced. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 130: 10/100/1000 Sgmii Interface

    DADDR HOSTCLK HOSTMIIMSEL HOSTOPCODE[1:0] HOSTREQ HOSTMIIMRDY HOSTRDDATA[31:0] HOSTWRDATA[31:0] HOSTEMAC1SEL DCREMACENABLE EMACDCRACK EMACDCRDBUS[0:31] DCREMACABUS[8:9] DCREMACCLK DCREMACDBUS[0:31] DCREMACREAD DCREMACWRITE DCRHOSTDONEIR UG074_3_60_012508 Figure 4-23: Ethernet MAC Configured in SGMII Mode www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 131: 10/100/1000 Sgmii Clock Management

    1.25 Gb/s or below, oversampling is used by the built-in MGT digital receiver to recover clock and data. Chapter 3 of UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide provides more details about the digital receiver oversampling operation. The inputs of the GT11CLK_MGT primitive connect to an external, high-quality reference clock with a frequency of 250 MHz specifically for the MGT.

  • Page 132: Sgmii Signals

    Reserved, tie to GND. RXBUFERR_# Input Reserved, tie to GND. RXCOMMADET_# Input Reserved, tie to GND. RXDISPERR_# Input Disparity error in RXDATA. RXLOSSOFSYNC[1:0]_# Input Reserved, tie to GND. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 133 Dynamic configuration input data bus. DEN_# Input Dynamic configuration bus enable when set to a logic 1. DWE_# Input Dynamic configuration write enable when set to a logic 1. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 134: Management Registers

    01 = 100 Mb/s. 5.11:10 Speed Read only 10 = 1000 Mb/s. 11 = Reserved. 5.9:1 Reserved Always returns 0s. Returns 0s 000000000 Reserved Always returns 1. Returns 1 www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 135: 1000Base-X Pcs/Pma

    The client interfaces can be either 8 bits or 16 bits wide. In 16-bit client mode, the Ethernet MAC can operate at 250 MHz, enabling a 2.5 Gb/s line rate. In this interface, not all the ports of the Ethernet MAC are used. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 136 HOSTCLK HOSTMIIMSEL HOSTOPCODE[1:0] HOSTREQ HOSTMIIMRDY HOSTRDDATA[31:0] HOSTWRDATA[31:0] HOSTEMAC1SEL DCREMACENABLE EMACDCRACK EMACDCRDBUS[0:31] DCREMACABUS[8:9] DCREMACCLK DCREMACDBUS[0:31] DCREMACREAD DCREMACWRITE DCRHOSTDONEIR UG074_3_63_012508 Figure 4-26: Ethernet MAC Configured in 1000BASE-X PCS/PMA Mode www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 137: Shim

    Because of small differences in the way the Virtex-II Pro and Virtex-4 FPGA RocketIO transceivers output the clock correction status and data when RXNOTINTABLE is asserted, a shim is needed to modify the received data from the Virtex-4 FPGA RocketIO transceiver (GT11) to the format that the EMAC is expecting.
  • Page 138 RXUSRCLK2 ‘0’ RXUSRCLK BUFG TXOUTCLK1 TXUSRCLK2 ‘0’ TXUSRCLK GT11 Client Logic EMAC# PHYEMAC#GTXCLK CLIENTEMAC#TXCLIENTCLKIN EMAC#CLIENTTXCLIENTCLKOUT CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXCLIENTCLKOUT UG074_3_80_030907 Figure 4-27: 1000BASE-X PCS/PMA (8-bit Data Client) Clock Management www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 139 The inputs of the GT11CLK_MGT primitive connect to an external, high-quality reference clock with a frequency of 250 MHz for 1.25 Gb/s and 2.5 Gb/s line rates. The output SYNCLK1OUT connects to the PLL reference clock input REFCLK1. TXOUTCLK1, www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...

  • Page 140: Pcs/Pma Signals

    CLIENTEMAC#DCMLOCKED. The lock signal ensures the Ethernet MAC does not operate until the MGT has achieved all the necessary locks. The phase-matched clock divider (PMCD) feature of certain Virtex-4 devices can be used to replace the client interface DCM. PCS/PMA Signals An Ethernet MAC wrapper has all the necessary pin connections to configure the primitive into 1000BASE-X PCS/PMA.
  • Page 141 Full Duplex duplex is not supported. The Ethernet MAC always returns a 0 100BASE-T2 for this bit because 100BASE-T2 half Returns 0 Half Duplex duplex is not supported. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 142 Organizationally Unique Identifier Returns 2.15:0 0000000000101000 Unique Identifier (OUI) from IEEE is 0x000A35. OUI(3-18) Organizationally Organizationally Unique Identifier Returns 3.15:10 110101 Unique Identifier (OUI) from IEEE is 0x000A35. OUI(19-24) www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 143 1 = Full-duplex mode is advertised. Full Duplex Read/Write 0 = Full-duplex mode is not advertised. 4.4:0 Reserved Always returns 0s, writes ignored. Returns 0s 00000 www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 144 1 = A new page is received. Page Received Self clearing 0 = A new page is not received. on read. Reserved Always returns 0s. Returns 0s 0000000 www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 145 The Ethernet MAC always returns a 0 1000BASE-T 15.13 for this bit because 1000BASE-T full Returns 0 Full Duplex duplex is not supported. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 146 If the interrupt is disabled, this bit is set to 0. The EMAC#CLIENTANINTERRUPT port is wired to this bit. 1 = Interrupt is enabled. 16.0 Interrupt Enable Read/Write 0 = Interrupt is disabled. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 147: Chapter 5: Miscellaneous Functions

    1.25 MHz CLIENTEMAC#TXCLIENTCLKIN Input Table 5-4: MII/GMII/RGMII Clock Frequency Clock Signals Direction 1000 Mb/s 100 Mb/s 10 Mb/s EMAC#CLIENTTXGMIIMIICLKOUT/ Output/ 125 MHz 25 MHz 2.5 MHz CLIENTEMAC#TXGMIIMIICLKIN Input www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...

  • Page 148: Transmit Clocking Scheme

    1000BASE-X mode, TX_GMII_MII_CLK is driven by PHYEMAC#GTXCLK, and the CLIENTEMAC#TXGMIIMIICLKIN clock is not used. When configured in MII mode, EMAC#CLIENTTXGMIIMIICLKOUT is derived from PHYEMAC#MIITXCLK. When configured in either GMII, RGMII, SGMII, or 1000BASE-X www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 149: Receive Clocking Scheme

    DCR using the host interface (see “Using the DCR Bus as the Host Bus” in Chapter Table 5-6 shows the register addresses for each of the two Ethernet MACs. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 150 Multicast Address Table Access (Word 0) 0x788 Multicast Address Table Access (Word 1) 0x78C Address Filter Mode 0x790 Notes: 1. HOSTEMAC1SEL acts as address bit 10 to select between EMAC0 and EMAC1. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 151: Auto-Negotiation Interrupt

    0)”) and is consequently only available when the optional MDIO Management Interface is present. Overview of Operation 1000BASE-X Standard Figure 5-3 illustrates the operation of 1000BASE-X auto-negotiation. Virtex-4 FPGA Link Partner Ethernet 1000BASE-X PCS/PMA or SGMII Sub-Layer Ethernet Auto-Neg Adv...
  • Page 152 By using the auto-negotiation interrupt port (see “Using the Auto-Negotiation Interrupt,” page 153). SGMII Standard Figure 5-4 illustrates the operation of SGMII auto-negotiation. SGMII capable Link Partner Virtex-4 FPGA BASE-T PHY Ethernet 1000BASE-X SGMII side BASE-T side PCS/PMA or SGMII Sub-Layer Twisted Ethernet...

  • Page 153: Auto-Negotiation Link Timer

    (for example, the CoreConnect™ bus interfacing to a MicroBlaze design or the PPC405 processor implemented in the Virtex-4 device). The operation of this port is enabled or disabled and cleared via Register 16 (see...
  • Page 154 Chapter 5: Miscellaneous Functions www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 155: Chapter 6: Use Models

    RTL. A Verilog LRM-IEEE 1364-2005 encryption-compliant simulator is required to use SecureIP. The SecureIP model of the Ethernet MAC is installed with Xilinx® tools and can be precompiled into UniSim and SimPrim libraries. These libraries are used for functional and timing simulations, respectively.

  • Page 156: Pinout Guidelines

    Chapter 6: Use Models Pinout Guidelines Xilinx recommends the following guidelines to improve design timing using the Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC: • If available, use dedicated global clock pins for the Ethernet MAC input clocks. • Use the column of IOBs located closest to the PowerPC processor and Ethernet MAC block.

  • Page 157: Interfacing To The Processor Dcr

    // Write the address of EMAC1 Flow Control register to the cntlReg // register mtdcr(0x0 + 14, 0x86C0); // Poll the RDYstatus register while ( !(mfdcr(0x0 + 15) & 0x00004000) ); www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 158 // Read the values returned of the Multicast Address Word0 and Word1 // registers (48-bit value) // from the dataRegMSW and dataRegLSW registers mult_addr_msw = mfdcr (0x0 + 12); mult_addr_lsw = mfdcr (0x0 + 13); www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 159 0x0 of EMAC0. MDIO must be enabled by writing to the management configuration register with the clock divider for MDC. Assuming the host frequency is 50 MHz and the divider is 0xA, results in an MDC frequency of 2.27 MHz. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 160 // Write the data to the PHY 0x0 register mtdcr(0x0 + 13, 0x00001140); // Write the decode address for MDIO Write Data to the cntlReg register mtdcr(0x0 + 14, 0x87B0); www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 161: Interfacing To An Fpga Fabric-Based Statistics Block

    Statistics blocks to both Ethernet MACs within the Ethernet MAC block. If statistics are required for only one Ethernet MAC, then the multiplexing between the statistics cores is simply replaced with a straight-through connection. www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com...
  • Page 162 Chapter 6: Use Models Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC LogiCORE Ethernet Statistics Example Design CLIENTEMAC0TXCLIENTCLKIN txclientclkin EMAC0CLIENTTXSTATS clienttxstats host_clk EMAC0CLIENTTXSTATSVLD clienttxstatsvld host_miim_sel EMAC0CLIENTTXSTATSBYTEVLD clienttxstatsbytevalid host_req CLIENTEMAC0RXCLIENTCLKIN rxclientclkin host_addr[8:0] EMAC0CLIENTRXSTATS[6:0] clienttxstatsvld[6:0] host_addr[9] EMAC0CLIENTRXSTATSVLD clientrxstatsvld host_rd_data[31:0] EMAC0CLIENTRXSTATSBYTEVLD clientrxstatsbytevalid LogiCORE Ethernet Statistics...

  • Page 163: When The Ethernet Mac Is Implemented With The Dcr Bus

    DCR Register EMAC Bus Signal [15] HOSTREQ [14:13] HOSTOPCODE[1:0] cntlReg[21], HOSTRDDATA [10] HOSTEMAC1SEL EMAC1Sel cntlReg[22:31], [9:0] HOSTADDR[9:0] Address Code HOSTMIIMRDY HOSTMIIMSEL dataRegLSW / HOSTWRDATA[31:0] HOSRTRDDATA[31:0] dataRegMSW HOSTMIIMSEL HOSTMIIMRDY www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 164 Ethernet Statistics blocks to both Ethernet MACs within the Ethernet MAC block. If statistics are required for only one Ethernet MAC, then the multiplexing between the statistics cores is simply replaced with a straight-through connection. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...
  • Page 165 Interfacing to an FPGA Fabric-Based Statistics Block Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC LogiCORE Ethernet Statistics Example Design CLIENTEMAC0TXCLIENTCLKIN txclientclkin EMAC0CLIENTTXSTATS clienttxstats host_clk EMAC0CLIENTTXSTATSVLD clienttxstatsvld host_miim_sel EMAC0CLIENTTXSTATSBYTEVLD clienttxstatsbytevalid host_req CLIENTEMAC0RXCLIENTCLKIN rxclientclkin host_addr[8:0] EMAC0CLIENTRXSTATS[6:0] clienttxstatsvld[6:0] host_addr[9] EMAC0CLIENTRXSTATSVLD clientrxstatsvld host_rd_data[31:0] EMAC0CLIENTRXSTATSBYTEVLD clientrxstatsbytevalid...
  • Page 166 Chapter 6: Use Models www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

  • Page 167: Chapter 7: Using The Embedded Ethernet Mac

    Accessing the Ethernet MAC from the CORE Generator tool Generating the Virtex®-4 FPGA embedded Ethernet MAC wrapper files using the CORE Generator tool greatly simplifies the use of the Virtex-4 FPGA Ethernet MAC. The Ethernet MAC is highly configurable, and not all pins/interfaces are required for every configuration.
  • Page 168 HDL hierarchy. See the block level wrapper file for more information. For further details on the Ethernet MAC wrappers, refer to DS307, Virtex-4 Embedded Tri- Mode Ethernet MAC Wrapper Data Sheet and GSG240, Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide.

  • Page 169: Appendix A: Ethernet Mac Timing Model

    This appendix explains the timing parameters associated with the Ethernet MAC block. It is intended to be used in conjunction with the Timing Analyzer (TRCE) report from Xilinx® software. Many signals enter and exit the Ethernet MAC block (as shown in Figure 2-3, page 21).

  • Page 170: Clock To Output Delays

    GMII/MII, the latency is 17 clock cycles at all speeds. RGMII has a latency of 20 clock cycles. SGMII has a latency of 20 clock cycles for 1 Gb/s and 15 clock cycles for 10/100 Mb/s. 1000BASE-X has a latency of 22 clock cycles. www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide...

  • Page 171: Timing Diagram And Timing Parameter Tables

    Data Output EMAC#CLIENTRXBADFRAME Tmaccko_CLKOUT Data Output EMAC#CLIENTRXCLIENTCLKOUT Tmaccko_RXD Data Output EMAC#CLIENTRXD Tmaccko_VALID Data Output EMAC#CLIENTRXDVLD Tmaccko_VALID Data Output EMAC#CLIENTRXDVLDMSW Tmaccko_FRAME Data Output EMAC#CLIENTRXFRAMEDROP Tmaccko_FRAME Data Output EMAC#CLIENTRXGOODFRAME www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 172 Data Hold DCREMACENABLE Tmacdck_ENABLE Data Setup DCREMACENABLE Tmacckd_HOST Data Hold HOSTADDR Tmacdck_HOST Data Setup HOSTADDR Tmacckd_HOST Data Hold HOSTEMAC1SEL Tmacdck_HOST Data Setup HOSTEMAC1SEL Tmacckd_HOST Data Hold HOSTMIIMSEL www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 173 Data Setup PHYEMAC#RXCHECKINGCRC Tmacckd_CORCNT Data Hold PHYEMAC#RXCLKCORCNT Tmacdck_CORCNT Data Setup PHYEMAC#RXCLKCORCNT Tmacckd_COMMA Data Hold PHYEMAC#RXCOMMADET Tmacdck_COMMA Data Setup PHYEMAC#RXCOMMADET Tmacckd_ERROR Data Hold PHYEMAC#RXDISPERR Tmacdck_ERROR Data Setup PHYEMAC#RXDISPERR www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 174 Data Hold PHYEMAC#CRS Tmacdck_CRS Data Setup PHYEMAC#CRS Tmacckd_RXD Data Hold PHYEMAC#RXD Tmacdck_RXD Data Setup PHYEMAC#RXD Tmacckd_VALID Data Hold PHYEMAC#RXDV Tmacdck_VALID Data Setup PHYEMAC#RXDV Tmacckd_ERROR Data Hold PHYEMAC#RXER www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...
  • Page 175 Data Output EMAC#CLIENTRXSTATS Tmaccko_VALID Data Output EMAC#CLIENTRXSTATSBYTEVLD Tmaccko_VALID Data Output EMAC#CLIENTRXSTATSVLD Tmaccko_RESET Data Output EMAC#PHYMGTRXRESET Tmaccko_VALID Data Output EMAC1CLIENTRXDVLD Tmaccko_VALID Data Output EMAC1CLIENTRXDVLDMSW Tmaccko_VALID Data Output EMAC1CLIENTRXDVREG www.BDTIC.com/XILINX Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.2) February 22, 2010...
  • Page 176 Appendix A: Ethernet MAC Timing Model www.BDTIC.com/XILINX www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.2) February 22, 2010...

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