Figure 3-23: Digital Receiver Example - Xilinx Virtex-4 RocketIO User Manual

R
•
In addition to the 1X Clock, the digital receiver can also generate a 4X and 2X clock based
on the fabric interface width specified by the user.
use for a given interface width. The parallel data is always frequency-locked and phase-
locked to these clocks.
Because the receiver is locked to reference, the inherent frequency difference between the
incoming data and the local PLL clock must be accommodated. In the Virtex-4 RocketIO
transceiver, this is accomplished by modulating the recovered clock. Typically, the
recovered clock is output to the FPGA fabric at the nominal frequency, but occasionally,
shorter clock periods are generated. The length of the shorter periods depends on the data
width chosen for the interface between the MGT and the FPGA logic. This is shown in
Table
Table 3-25: Variation of Recovered Clock Period
The FPGA logic driven by this clock must be able to run at the clock frequency determined
by the shorter period of the recovered clock.
In the example given in
15.55 MHz. The normal clock period for this frequency is 64 ns; however, the 12.5% shorter
clock period is 56 ns, which translates into a clock frequency of 17.9 MHz.
This variation becomes more important at smaller interface widths and higher interface
speeds. For example, changing to a 1-byte interface between MGT and FPGA in
Figure 3-23
shorter clock period (12 ns) translates into a recovered clock frequency of 83.3 MHz.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Digital receiver output clock = 1X clock = 124.4 ÷ 8 (sampling rate) = 15.55 Mhz (line
rate/parallel data width)
PCS
32/40 bit
parallel data
40-bit parallel data
15.55 MHz
Parallel clock
locked to data

Figure 3-23: Digital Receiver Example

3-25.
Interface Width
(8x Oversampling)
1 Byte
2 Byte
4 Byte
Figure
would result in a nominal speed of 62.2 MHz and period of 16 ns. The 25%
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Digital CDR
32/40 bit
Sample Processor
parallel data
and Data Tracking
(four 8-bit/
10-bit symbols)
(8X Oversampling Mode)
Parallel clock
(124.4 MHz = 4.976G/40)
Table 3-26
Output Clock Period
Clock Rate Variation [%]
4X
2X
1X
3-23, the nominal frequency of the recovered clock is
Digital Receiver
Rx PMA
PLL*
2.488G CLK
= 4.976 Gb/s
SIPO
* PLL configured to remain
locked to Reference Clock
ug076_ch3_22_040706
defines the clock frequency to
Speed Margin
Required [%]
25 133
12.5 114
12.5 114
155.5 MHz
Reference
Clock
RXP/RXN
(0.622 Gb/s)
135