Resets; Txpmareset; Rxpmareset - Xilinx Virtex-4 RocketIO User Manual

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Resets

The MGT has several different resets shown in
portions of the MGT. RXRESET and TXRESET reset the PCS portions of the transceiver.
RXPMARESET and TXPMARESET reset the PMA portion of the transceiver. There are also
two CRC logic resets (see
Table 2-9: MGT Reset Signals

TXPMARESET

The TXPMARESET port is used to reset the PMA and reinitialize the PMA functions.
Asserting this signal resets PLL control logic and the internal PMA dividers. It also causes
the transmit PLL lock signal TXLOCK to be deasserted and forces the TX PLL into
calibration. During the time TXPMARESET is asserted, the PMA parallel clocks
TXOUTCLK1 and TXOUTCLK2 output to the fabric remains at a constant 0. The data that
remains in the parallel-to-serial converter after asserting TXPMARESET is transmitted on
the serial lines (TXN/TXP ports). Since TXPMARESET forces the PLL into calibration, the
frequency of the transmitted data is not guaranteed to be correct until the PLL is locked.
Below is a list of requirements for TXPMARESET:
•
•
The parallel clock dividers used to generate each transmitter's TXOUTCLK1 and
TXOUTCLK2 clocks are controlled by the TXPMARESET ports of MGTA and MGTB.
Calibration of the shared transmitter VCO is reset only by the TXPMARESET signal of
MGTA. (The MGT tile contains one Tx PLL and two separate parallel clock dividers.)
If the design uses:
•
•

RXPMARESET

The RXPMARESET port is used to reset the PMA and reinitialize the PMA functions.
Asserting this signal resets the PLL control logic. It also causes the receive PLL lock signal
RXLOCK to be deasserted and forces the RX PLL into calibration. During the time
RXPMARESET is asserted, the PMA parallel clocks RXRECCLK1 and RXRECCLK2 output
to the fabric does not remain at a constant 0, but its frequency is incorrect because the PLL
is not locked.
Following is a list of requirements for RXPMARESET:
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Chapter 5, "Cyclic Redundancy Check
Reset
RXCRCRESET
TXCRCRESET
RXPMARESET
TXPMARESET
TXRESET
RXRESET
Set TXPMARESET signal to logic 1 at startup for a minimum of three USRCLK cycles
(based on internal data width).
Do not use the output clocks of the MGT for clocking this reset.
MGTA only: apply a TXPMARESET on MGTA.
MGTB only: apply a TXPMARESET on both MGTA and MGTB.
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Table 2-9. The resets affect different
Description
Resets the receiver CRC logic.
Resets the transmitter CRC logic.
Resets the receiver PMA logic.
Resets the transmitter PMA logic.
Resets the transmitter PCS logic.
Resets the receiver PCS logic.
Resets
(CRC)").
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