Xilinx Virtex-4 RocketIO User Manual page 318

Appendix C: Dynamic Reconfiguration Port
Table C-26: Dynamic Reconfiguration Port Memory Map: MGTB Address 77–7B
Bit
77
15
14
CHAN_BOND_SEQ_1_MASK
[3:0]
13
12
11
10
9
8
7
CHAN_BOND_SEQ_1_4
6
[10:0]
5
4
3
2
1
0 CHAN_BOND_SEQ_1_3[10]
Notes:
1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
318
Def 78 Def
RESERVED
N/A
VCODAC_INIT
(1)
[9:0]
N/A
0
SLOWDOWN_CAL
(1)
[1:0]
0
(1)
BYPASS_FDET
N/A
LOOPCAL_WAIT
(1)
[1:0]
www.xilinx.com
Address
79 Def
RXASYNCDIVIDE
PCOMMA_32B_VALUE
N/A
[31:16]
(1)
7A Def 7B
0
0
0
RESERVED
[5:0]
0
0
0
PMA_BIT_SLIP 0
X
RESERVED
[1:0]
[15:0]
X
X
X
X
RXCLKMODE
[5:0]
X
X
X
RXLB 0
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
N/A