Xilinx Virtex-4 RocketIO User Manual page 307

R
Table C-15: Dynamic Reconfiguration Port Memory Map: MGTB Address 40–44
Bit
40 Def
15
14
13
12
11
10
9
8
RXCRCINITVAL
N/A
[15:0]
7
6
5
4
3
2
1
0
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
41 Def 42
0
0
0
0
RESERVED
[7:0]
0
0
0
0
RESERVED
[15:0]
0 COMMA32
0 PCOMMA_DETECT
0 MCOMMA_DETECT
0 DEC_VALID_COMMA_ONLY
0 DEC_PCOMMA_DETECT
0 DEC_MCOMMA_DETECT
0
ALIGN_COMMA_WORD
[1:0]
0
www.xilinx.com
Address
Def 43
RESERVED
CLK_COR__8B10B_DE
CLK_CORRECT_USE
CLK_COR_SEQ_LEN
[2:0]
CLK_COR_SEQ_DROP
CLK_COR_SEQ_2_USE
N/A
TXCLK0_INVERT_PMALEAF
RESERVED
CLK_COR_MAX_LAT
[5:0]
Memory Map
Def 44 Def
0
0
0
0
0
0
0
0
RXEQ
N/A
[15:0]
0
0
0
0
0
0
0
0
307