Hspice; Smartmodel Simulation Considerations; After Reset Or Power-Up; Reference Clock Period Restriction - Xilinx Virtex-4 RocketIO User Manual

Chapter 7: Simulation and Implementation

HSPICE

HSPICE is a simulation model for the analog portions of the MGT design. To obtain these
HSPICE models, go to the SPICE Suite Access web page at:
http://support.xilinx.com/support/software/spice/spice-request.htm.

SmartModel Simulation Considerations

After Reset or Power-Up

Power-up or reset sequences affect simulation.
After reset or power-up, the inputs TX/RXCLKSTABLE going into the MGT must be
asserted. (These can be driven by a DCM locked signal, for example.) The TX/RXLOCK
signals do not assert if the TX/RXCLKSTABLE signals do not go High. The
TX/RXCLKSTABLE signals start the frequency calibration process whereby the PLL lock
is determined.
For more information, refer to section

Reference Clock Period Restriction

Due to simulator and HDL limitations, the reference clock period must be rounded to the
nearest 0.1 ns. For example, in Fibre Channel 2x and 4x with a reference clock of
212.5 MHz, the reference clock period must be changed from 4.71 ns to 4.7 ns.
The RocketIO Wizard generates the correct reference clock period for all configurations.

RXP/RXN Period Restrictions

The period of the signals provided to the RXP/RXN RocketIO inputs must be an even
number in picoseconds. This is due to specific timescale implementations within the
SmartModel. If this is not done, the Receive data can be corrupted.

Reset After Changing Clock Attributes

If any of the attributes pertaining to clocks (see
a PMARESET should be issued. Follow this initialization sequence to issue a PMARESET:
1.
2.
3.
4.
5.
6.
The reset minimum widths are specified as three TX/RXUSRCLK cycles. Each clock
domain clocks in the reset and releases it. Three TX/RXUSRCLKs should be sufficient in all
cases. Five TX/RXUSRCLK cycles are needed to allow the reset to be deasserted internally.
180
Ensure the inputs TX/RXCLKSTABLE going into the MGT are asserted.
Issue a TX/RXPMARESET that lasts a minimum of three TX/RXUSRCLK cycles.
Wait for TX/RXLOCK.
Note:
In the absence of a serial data stream, the receiver repeatedly locks and unlocks.
Issue a TX/RXRESET that lasts a minimum of three TX/RXUSRCLK cycles.
Wait for a minimum of five TX/RXUSRCLKs.
Begin normal data transmission and reception.
www.xilinx.com
"RXCLKSTABLE and TXCLKSTABLE," page
Table 1-11, page
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
82.
50) are changed,
R