Xilinx Virtex-4 RocketIO User Manual page 296

Appendix C: Dynamic Reconfiguration Port
Table C-4: Dynamic Reconfiguration Port Memory Map: MGTA Address 4A–4E
Bit
4A Def
15
14
13
12
SH_INVALID_CNT_MAX
11
10
9
8
RESERVED
N/A
[15:0]
7
6
5
4
3
2
1
0
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
296
4B Def
TXDAT_PRDRV_DAC
TXASYNCDIVIDE[0]
[7:0]
TXPOST_TAP_DAC
N/A
SH_CNT_MAX
[7:0]
Table C-28, page 320 for details.
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Address
(1)
4C Def
1
(2)
[1:0]
1
X
TXPOST_TAP_PD 1
0
1
1
[4:0]
1
0
0
RESERVED
[1:0]
0
1
0
TXDAT_TAP_DAC
1
[4:0]
1
0
4D Def 4E
RXCMADJ
[1:0]
RXCDRLOS
[5:0]
UNUSED
N/A
[15:0]
RESERVED
RXDCCOUPLE
RESERVED
RXLKADJ
[4:0]
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
N/A
0
0
0
0
0
0
N/A
0
0
0
0
0
0
0