Powering Unused Mgts - Xilinx Virtex-4 RocketIO User Manual

Chapter 6: Analog and Board Design Considerations

Powering Unused MGTs

Important: All MGTs in the FPGA, whether instantiated in the design or not, must be
connected to power and ground. Unused MGTs should be connected as follows:
•
•
•
•
Passive filtering of unused supply voltage pins is not required unless certain clock routing
layouts make it necessary.
AVCCAUXMGT must always be powered to nominal 2.5V. Filtering must be used in any
tile that uses a GT11CLK_MGT or MGT, or when SYNCLK1/2 passes through that tile.
Since clocking resources for each MGT tile are powered from AVCCAUXRXB and
AVCCAUXMGT, careful placement of used/unused MGTs must be observed to reduce the
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Figure 6-5: Layout for Power Filtering Network
AVCCAUXTX and AVCCAUXRX should be connected to 1.2V.
V and V should be connected to 1.2V (recommended). However, V
TTX TRX
left floating (unconnected).
MGTCLK_P_* / MGTCLK_N_* should be tied to a differential zero (the _N signal
tied to 1.2V and the _P signal tied to GND), or they can be left floating (unconnected).
TXP/TXN and RXP/RXN pins can be left floating (unconnected).
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Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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