Xilinx Virtex-4 RocketIO User Manual page 316

Appendix C: Dynamic Reconfiguration Port
Table C-24: Dynamic Reconfiguration Port Memory Map: MGTB Address 6D–71
Bit
6D Def 6E
15 0
14 0
13 0
12 0
11 0
CHAN_BOND_SEQ_2_3
[9:0]
10 0
9 0
8 0
UNUSED
[15:0]
7 0
6 0
5 0
4 0
3 0
CHAN_BOND_SEQ_2_2
[10:5]
2 0
1 0
0 0
Notes:
1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
316
Address
Def 6F Def
CHAN_BOND_SEQ_1_3
[9:0]
N/A N/A
CHAN_BOND_SEQ_1_2
[10:5]
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70 Def
(1)
BYPASS_CAL
FDET_HYS_CAL
[2:0}
FDET_LCK_CAL
[2:0}
N/A
PCOMMA_32B_VALUE
FDET_HYS_SEL
[2:0}
FDET_LCK_SEL
[2:0}
(1)
VCO_CTRL_ENABLE
0
CYCLE_LIMIT_SEL
(1)
[1:0]
0
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
71 Def
N/A
[15:0]