Xilinx Virtex-4 RocketIO User Manual page 98

Chapter 2: Clocking, Timing, and Resets
Below are the steps describing the flow chart in
1.
2.
3.
4.
5.
6.
7.
98
RX_SYSTEM_RESET: Upon RX system reset on this block, go to the RX_PMA_RESET
state.
RXPMARESET == 0
RXRESET == 0
RXSYNC == 0
RX_PMA_RESET: Assert RXPMARESET for three RXUSRCLK cycles.
RXPMARESET == 1
RXRESET == X
RXSYNC == 0
RX_WAIT_LOCK: Stall until RXLOCK is High and until the clocks on RXUSRCLK
and RXUSRCLK2 are stable (rx_usrclk_stable == 1), then wait for 16K (16 x 1024)
REFCLK cycles. The amount of wait from the REFCLK cycles covers the 12,000
RXUSRCLK2 cycles required by the RXSYNC timing waveform (see
"RXSYNC Timing," page
for information on the 16K REFCLK cycles requirement.
RXPMARESET == 0
RXRESET == X
RXSYNC == 0
RX_SYNC: Assert RXSYNC for 64 synchronization cycles. If RXLOCK is deasserted,
go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == X
RXSYNC == 1
RX_PCS_RESET: Assert RXRESET for three RXUSRCLK cycles. If RXLOCK is
deasserted, go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == 1
RXSYNC == 0
RX_WAIT_PCS: Wait for five RXUSRCLK cycles after deassertion of RXRESET. If
RXLOCK is deasserted, go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == 0
RXSYNC == 0
RX_ALMOST_READY: Wait for 64 RXUSRCLK cycles with no error on the received
data and RXLOCK High for this amount of time; this is to ensure that the RX MGT is
stable after start-up and ready for data reception. If RXLOCK is deasserted, go back to
RX_WAIT_LOCK state. If an rx_error is detected while RXLOCK is High, the reset
sequence block should apply RXRESET by cycling back to the RX_PCS_RESET state. If
this step occurs 16 times as monitored by the rx_pcs_reset_cnt counter, apply a
RXPMARESET by cycling back to the RX_PMA_RESET state.
RXPMARESET == 0
RXRESET == 0
RXSYNC == 0
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Figure
228). Also, see "RX Reset Sequence Background," page 100
2-22:
Figure 8-22,
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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