Use Models - Xilinx Virtex-4 RocketIO User Manual

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Use Models

Table 8-9: TX Use Models: Low-Latency Buffer Bypass w/out Channel Deskew
Internal PCS clock
TX_3A
dividers to derive
FALSE
TXUSRCLK from
TX_3B
TXUSRCLK2 only.
Notes:
1. All cases addressed assume a 4-byte fabric width. Refer to section
2. PCS TXCLK used as clock synchronization source.
3. TXSCRAM64B66BUSE and TXGEARBOX64B66BUSE are always to be set to the same value.
4. TXSYNC functionality must be used in order to sync the PCS/PMA clocks.
5. MGTA/MGTB Register 0x43[7]=1 always for TX Low Latency. This can be accomplished with a Read-Modify-Write Operation
via the Dynamic Reconfiguration Port. Alternatively, this can be achieved by adding the constraint TXCLK0_INVERT_PMALEAF =
"TRUE" to the UCF file. The COREGen RocketIO Wizard generates this constraint when choosing to bypass the buffer to enable Low
Latency.
6. 64B/66B encoding/decoding is not supported.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Partial Bypass uses
1
8B/10B Encode
Full PCS Bypass
0
(8B/10B Bypass)
"Clocking," page 198
www.xilinx.com
Transmit Latency and Output Skew
(6)
PORTS ATTRIBUTES
0 0 0 10
REQ'D FALSE 11
0 0 0 01
for 2 byte or 1 byte fabric width.
TRUE
(Note 5)
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