Figure 2-16: Flow Chart Of Tx Reset Sequence Where Tx Buffer Is Bypassed; Transmit Reset Sequence: Tx Buffer Bypassed - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets

Transmit Reset Sequence: TX Buffer Bypassed

Figure 2-16
bypassed.
88
provides a flow chart of the transmit reset sequence when the TX buffer is
TX_SYSTEM_RESET
system_reset==0
TX_PMA_RESET
TXPMARESET==1 for
3 TXUSRCLK cycles
TX_WAIT_LOCK
tx_usrclk_stable==1 && TXLOCK==1
for 12,000 TXUSRCLK2 cycles
TXLOCK==0
TX_SYNC
TXSYNC==1 for
64 synchronization clock cycles
TXLOCK==0
TX_PCS_RESET
TXRESET==1 for
3 TXUSRCLK cycles
TXLOCK==0
TX_WAIT_PCS
5 TXUSRCLK cycles
TXLOCK==0
TX_ALMOST_READY
tx_align_err==0 && TXLOCK=1
for 64 TXUSRCLK cycles
TXLOCK==0
TX_READY

Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed

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tx_sync_cnt==16 &&
tx_align_err==1 &&
TXLOCK==1
tx_sync_cnt < 16 && tx_align_err==1 && TXLOCK==1
tx_align_err==1 && TXLOCK==1
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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ug076_ch2_17_060606