Xilinx Virtex-4 RocketIO User Manual page 150

Chapter 4: PMA Analog Design Considerations
Table 4-4: Transmit Calibration (Continued)
Table 4-5: Receive Calibration
Table 4-6
FDET_LCK_CAL/RXFDET_LCK_CAL during calibration, and of attributes
FDET_HYS_SEL/RXFDET_HYS_SEL and FDET_LCK_SEL/RXFDET_LCK_SEL after
calibration has been completed and normal operation started. These attributes set the PLL
accuracy and determine whether the PLL is in lock or out of lock. For the RX side in analog
CDR mode, these settings determine when the PLL starts to track input data (in lock) and
when it tracks the reference clock (out of lock) during normal operation.
The Lock setting alone is used to specify a maximum percentage difference between the
PLL and the reference clock/data that results in acquisition of lock. After lock as been
acquired, the Hysteresis setting (columns 3 through 10) determines, in conjunction with
the Lock setting, the percentage difference between the PLL and reference clock/data
above which lock is lost. In other words, acquisition of lock is based on the Lock setting
without hysteresis (a Hysteresis setting of 000); loss of lock is based on the Lock setting
extended by the amount of additional frequency divergence (hysteresis) that is tolerated.
Referring to
frequencies differ from each other by 0.781% or less. The acquired lock is lost when the PLL
and the reference clock/data frequencies differ from each other by 6.25% or more.
In selecting the calibration and normal operation lock and hysteresis settings, always set
the normal operation ranges tighter than the calibration ranges.
150
Attribute
TXFDCAL_CLOCK_DIVIDE
Attribute
RXFDET_HYS_CAL
RXFDET_HYS_SEL
RXFDET_LCK_CAL
RXFDET_LCK_SEL
RXVCODAC_INIT
RXFDCAL_CLOCK_DIVIDE
explains the usage of attributes FDET_HYS_CAL/RXFDET_HYS_CAL and
Example:
Lock setting = 101
Hysteresis setting = 011
Table 4-6, lock is acquired when the PLL and the reference clock/data
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Recommended
Setting
Reference clock ≤ 250 MHz
NONE
Reference clock > 250 MHz
TWO
Reference clock > 500 MHz
FOUR
Recommended
Setting
Use RocketIO
The settings for this attribute depend on
wizard to get
the system line rate and reference clock
recommended
frequency.
settings.
Reference clock ≤ 250 MHz
NONE
Reference clock > 250 MHz
TWO
Reference clock > 500 MHz
FOUR
Virtex-4 RocketIO MGT User Guide
System Conditions
System Conditions
UG076 (v4.1) November 2, 2008
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