Xilinx Virtex-4 RocketIO User Manual page 69

R
Table 2-4: TX PMA Attribute Values
Notes:
1. See
Table 2-5: Supported Transmitter PLL Divider Combinations
Notes:
1. For lower wide-band jitter generation, choose a reference clock frequency that uses a lower feedback
2. Line Rate = VCO Frequency*2/TXOUTDIV2SEL.
3. Reference Clock = VCO Frequency/TXPLLNDIVSEL
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Attribute
TXPLLNDIVSEL
TXOUTDIV2SEL
TXASYNCDIVIDE
TXCLKMODE
TXOUTCLK1_USE_SYNC
Figure 2-12 for application-specific settings.
Line Rate (Mb/s)
Min Max
4960 6500
2480 4300
3100 4300
1240 2150
622 1075
divider.
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(1)
Available
Values
Transmit PLL feedback divide. This value
becomes the PLL multiplication factor for the
reference clock.
Transmitter PLL output divide. DRP values are:
40, 32, 20, 16,
40 = 1010
10, 8
32 = 1000
20 = 0110
16 = 0100
10 = 0010
8 = 0000
TXOUTDIV2SEL value = DRP value:
1 = 0001
2 = 0010
1, 2, 4, 8, 16, 32
4 = 0011
8 = 0100
16 = 0101
32 = 0110
Async Divide:
00= Divide by 1
00, 01,
01= Divide by 2
10, 11
10= Divide by 4
11= Divide by 4
0110, 0100,
Divider Control for synchronous PCS TXCLK
1000, 1001,
and asynchronous PCS TXCLK. Refer to
0000, 1110,
Figure 2-4.
1111
FALSE:
TXOUTCLK1 = Asynchronous PCS TXCLK
TRUE, FALSE
TRUE:
TXOUTCLK1 = Synchronous PCS TXCLK
Output Divider Feedback Divider
TXOUTDIV2SEL TXPLLNDIVSEL
1
2
2 16, 20
4 8, 10, 16, 20
8 8, 10, 16, 20
Clock Distribution
Definition
VCO Frequency (MHz)
Min
8, 10 2480
8, 10 2480
3100
2480
2488
Max
3250
4300
4300
4300
4300
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