Xilinx Virtex-4 RocketIO User Manual page 46

Chapter 1: RocketIO Transceiver Overview
Table 1-6: RocketIO MGT PCS Ports (Continued)
Port
TXDATAWIDTH
TXINTDATAWIDTH
Status/Clocks
RXBUFERR
RXRESET
RXSTATUS
RXUSRCLK
RXUSRCLK2
TXBUFERR
TXRESET
TXUSRCLK
TXUSRCLK2
Notes:
1. 64B/66B encoding/decoding is not supported.
46
I/O Port Size
Indicates width of FPGA parallel bus. (See
I 2
page 104.)
Sets the internal mode of the transmit PCS:
I 2
2'b10 = 32-bit
2'b11 = 40-bit
Provides status of the receiver buffer. If raised to a logic 1, an
O 1 overflow/underflow has occurred. When this bit becomes set,
it can only be reset by asserting RXRESET
Synchronous RX PCS reset that "recenters" the receive ring
buffer. It also resets 8B/10B decoder, comma detect, channel
I 1 bonding, clock correction logic, digital oversampling CDR,
and other internal receive registers. It does not reset the
receiver PLL or transmit PCS.
RXSTATUS[5] indicates a receiver has successfully completed
channel bonding when raised to logic 1. RXSTATUS[4:0]
O 6 indicates the status of the receive buffer pointers, channel
bonding skew, and clock correction events. See
Indication" in Chapter 3
Clock that is used for reading the RX ring buffer. It also clocks
I 1 CHBONDI and CHBONDO in and out of the transceiver.
Typically, the same as TXUSRCLK.
Clock output that clocks the receive data and status between
I 1 the transceiver and the FPGA core. Typically, the same as
TXUSRCLK2.
Provides status of the transmission buffer. If raised to logic 1,
O 1 an overflow/underflow has occurred. When this bit becomes
set, it can only be reset by setting TXRESET to logic 1.
Synchronous TX PCS reset that "recenters" the transmit buffer.
It also resets 8B/10B encoder and other internal transmission
I 1
registers. It does not reset the PMA including the PLL or
receive PCS.
Clock input that is clocked with the reference clock. This clock
I 1 is used for writing the TX buffer and must be frequency-
locked to the reference clock.
Clock input that clocks the transmit data and status between
I 1 the FPGA core and the transceiver. Typically the same as
RXUSRCLK2.
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Definition
Table 3-1,
section"Status
for details.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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