Figure 8-13: Tx Low Latency Buffer Bypass Mode: Use Model Tx_3A - Xilinx Virtex-4 RocketIO User Manual

Multi-gigabit transceiver

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Chapter 8: Low-Latency Design

Use Models TX_3A and TX3B

TXDATA (2,4,8B)

shows the buffer bypass mode flow through the TX using 8B/10B encoding.

TX_CLOCK_DIVIDER

Note: (1) 64B/66B encoding/decoding is not supported.

Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A

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TXCLK0_FORCE_PMACLK,

TX_CLOCK_DIVIDER

TXENC8B10BUSE,

TX_BUFFER_USE

TXENC64B66BUSE

PCS Dividers &

Clock Control

TXSCRAM64B66BUSE,

TXGEARBOX64B66BUSE,

ug076_ch8_09_071907

Virtex-4 RocketIO MGT User Guide

UG076 (v4.1) November 2, 2008

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