Skew; Reset; Figure 8-11: Tx Low Latency Buffered Mode: Use Model Tx_2H - Xilinx Virtex-4 RocketIO User Manual

R
Figure 8-11
10GBASE-R encoding, 10GBASE-R GearBox, and 64B/66B Scrambler.
TXDATA (2,4,8B)

Skew

See section

Reset

For the use models using GREFCLK to synchronize the MGTs, the user must ensure that
the TX phase buffer included in the PCS comes out of reset across the MGTs on the same
PCS TXCLK so the latency through the TX buffers is consistent.
To ensure this, the TXRESET should be deasserted on the negative edge of TXUSRCLK.
Refer to section
skew.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
shows the buffered-mode flow through the TX bypassing 8B/10B encoding,
TX_CLOCK_DIVIDER
TXUSRCLK
÷2
÷4
TXUSRCLK2
TXUSRCLK2 TXUSRCLK
TXOUTCLK1/
TXOUTCLK2
8B/10B
Encode
10GBASE-R
TXCHARISK
Encode (1)
ETC.
PCS
Note: (1) 64B/66B encoding/decoding is not supported.

Figure 8-11: TX Low Latency Buffered Mode: Use Model TX_2H

"TX Channel Skew using TXSYNC," page
"Resets" in Chapter 2
www.xilinx.com
TXCLK0_FORCE_PMACLK,
TX_CLOCK_DIVIDER
00
10 01 11
010 001
PCS
TXCLK
00
F
10
8x40 bit
Ring
T
Buffer
01
TXENC8B10BUSE,
TX_BUFFER_USE
TXENC64B66BUSE
for details on resetting multiple MGTs to minimize
Transmit Latency and Output Skew
011 000 1XX
PMA TXCLK0
PCS Dividers &
Clock Control
Phase Align
0001
0010
0000
10GBASE-R
Gearbox (1)
64B/66B
1100
Scrambler (1)
TXSCRAM64B66BUSE,
TXGEARBOX64B66BUSE,
TXDATA_SEL
215.
TXP
PISO
TXN
PMA
ug076_ch8_22_071907
209