Xilinx Virtex-4 RocketIO User Manual page 295

R
Table C-3: Dynamic Reconfiguration Port Memory Map: MGTA Address 45–49
Bit
45 Def
15
14
13
12
11
10
9
8
UNUSED
0
[15:0]
7
6
5
4
3
2
1
0
Notes:
1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
46 Def
RXDIGRESET 0
0
RXFECONTROL2
0
(1)
[2:0]
0
(1)
RXCPTST 0
(1)
RXPDDTST 1
(1)
RXACTST 0
(1)
RXAFETST 0
0
RXFECONTROL1
(1)
[1:0]
0
(1)
RXLKAPD 0
(1)
RXRSDPD 0
RXRCPPD 0
RXRPDPD 0
RXAFEPD 0
RXPD 0
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Address
47 Def 48
0
0
0
0
0
0
0
0
RXEQ RXCRCINITVAL
[15:0] [31:16]
0
0
0
0
0
0
0
0
Memory Map
Def 49 Def
RESERVED
N/A N/A
[15:0]
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