Reset - Xilinx Virtex-4 RocketIO User Manual

R
Figure 8-21
well as decoding.
RXP
RXN

Reset

Refer to section
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
shows the full PCS bypass flow through the RX, bypassing comma detection as
RXCLK0_FORCE_PMACLK, LOOPBACK[0],
RX_CLOCK_DIVIDE
1XXX 0100
PMA RXCLK0
Sync Control Logic
10GBASE-R
Block
Comma
SIPO
Sync (1)
Detect
Align
PCS
Dividers
& Phase
Align
Clock
Control
PMA
ENMCOMMAALIGN RXBLOCKSYNC64B66BUSE,
ENPCOMMAALIGN RXCOMMADETUSE
Note: (1) 64B/66B encoding/decoding is not supported.
Figure 8-21: RX Low Latency Buffer Bypass Mode: Use Model RX_2C
"Resets" in Chapter 2
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PMA TXCLK0
00 11 01 10
0000 0X11 0X01 0X10
PCS
RXCLK
Channel Bonding &
Clock Correction
8B/10B
10
11
Decode
13x64 bit
Ring
64B/66B
Buffer
01 01
Descram (1)
00 00
RXDEC8B10BUSE,
RXDESCRAM64B66BUSE
for more details.
RX Latency
RX_CLOCK_DIVIDER
÷2
÷4
RXUSRCLK
RXUSRCLK2
T 000
10GBASE-R
100
F
Decode (1)
011
010
001
PCS
RX_BUFFER_USE RXDEC64B66BUSE,
RXDATA_SEL
ug076_ch8_17_071907
RXUSRCLK
RXUSRCLK2
RXDATA
RXCHARISK
...ETC
RXRECCLK1/
RXRECCLK2
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