ABB Relion 670 Series Technical Reference Manual page 92

Section 4
Basic IED functions
86
Fast clock synchronization mode
At startup and after interruptions in the GPS or IRIG B time signal, the clock deviation
between the GPS time and the internal differential time system can be substantial. A
new startup is also required after for example maintenance of the auxiliary voltage system.
When the time difference is >16μs, the differential function is blocked and the time
regulator for the hardware clock automatically uses a fast mode to synchronize the
clock systems. The time adjustment is made with an exponential function, that is, big
time adjustment steps in the beginning, then smaller steps until a time deviation
between the GPS time and the differential time system of >16μs has been reached.
Then the differential function is enabled and the synchronization remains in fast mode
or switches to slow mode, depending on the setting.
Slow clock synchronization mode
During normal service, a setting with slow synchronization mode is normally used,
which prevents the hardware clock to make too big time steps, >16µs, emanating from
the differential protection requirement of correct timing.
Synchronization principle
From a general point of view synchronization can be seen as a hierarchical structure. A
function is synchronized from a higher level and provides synchronization to lower levels.
Synchronization from
a higher level
Optional synchronization of
modules at a lower level
IEC09000342 V1 EN
Figure 26: Synchronization principle
A function is said to be synchronized when it periodically receives synchronization
messages from a higher level. As the level decreases, the accuracy of the
synchronization decreases as well. A function can have several potential sources of
synchronization, with different maximum errors. This gives the function the possibility
Function
IEC09000342-1-en.vsd
1MRK505222-UUS C
Technical reference manual