ABB Relion 670 Series Technical Reference Manual page 875

1MRK505222-UUS C
Technical reference manual
ModeOutput1
Input 1
OR
ModeOutput2
Input 17
OR
ModeOutput3
ANSI10000055 V2 EN
Figure 434: Trip matrix internal logic
Output signals from TMAGGIO are typically connected to other logic blocks or
directly to output contacts in the IED. When used for direct tripping of the circuit
breaker(s) the pulse time delay shall be set to approximately 0.150 seconds in order to
obtain satisfactory minimum duration of the trip pulse to the circuit breaker trip coils.
0-OnDelay
0
0-OnDelay
0
0-OnDelay
OR
0
Section 14
PulseTime
t
AND
OR
AND
0
0-OffDelay
PulseTime
t
AND
OR
AND
0
0-OffDelay
PulseTime
t
AND
OR
AND
0
0-OffDelay
ANSI10000055-1-en.vsd
Logic
Output 1
Output 2
Output 3
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