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Power
Figure 26. Power Timings for External Regulator
Table 29. Timing Parameters for External Regulator
Timing Parameter
13.2
Configuration for Internal VR
In some applications, it may be necessary to use only one internal platform VR from
the SoC. The following guidelines describe how to terminate the unused internal VR
signals in this implementation:
1. Tie PWR_REG_EN signal to reference plane (GND).
2. Connect the following unused internal VR signals to reference plane (GND):
3. Leave the following unused VR signals VCCOUT_ESRx_yPz (no connect):
4. Connect both VSS_GNDSENSE_ESRx signals to reference plane (GND).
5. VCC_IO_AON can use either internal VR or external VR as the power source.
June 2017
Document Number: 334715-004EN
t
BATT_OPM
t
BATT_AON
For 3.3V, connect VCC_SENSE_ESR1 and VCCOUT_QLR1_3P3.
For 1.8V, connect VCC_SENSE_ESR2 and VCCOUT_QLR2_1P8.
For 3.3V, leave VCCOUT_PLAT_3P3_3P3.
For 1.8V, leave VCCOUT_PLAT_1P8_1P8.
Minimum
0 us
200 us
Intel® Quark™ SE Microcontroller C1000
Maximum
100 us
2 ms
Platform Design Guide
53
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