Interrupts And Interrupt Vector; Fixed Vector Tables - Renesas M16C FAMILY series Hardware Manual
16-bit single-chip microcomputer
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9.2 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2 shows the interrupt vector.
Vector address (L)
Vector address (H)
Figure 9.2 Interrupt Vector
9.2.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to 17.3 Flash Memory Rewrite Dis-
abling Function.
Table 9.1 Fixed Vector Tables
Interrupt source
Undefined instruction FFFDC
Overflow
BRK instruction
Address match
Single step
(1)
Watchdog timer,
Oscillation stop and
re-oscillation detection,
Low voltage
detection
________
DBC
(1)
_______
NMI
Reset
(2)
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. The b3 to b0 in the address FFFFF
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Vector table addresses
Address (L) to address (H)
to FFFDF
16
FFFE0
to FFFE3
16
FFFE4
to FFFE7
16
FFFE8
to FFFEB
16
FFFEC
to FFFEF
16
FFFF0
to FFFF3
16
FFFF4
to FFFF7
16
FFFF8
to FFFFB
16
FFFFC
to FFFFF
16
16
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Low-order address
Middle-order address
0 0 0 0
High address
0 0 0 0
Remarks
Interrupt on UND instruction
16
Interrupt on INTO instruction
16
If the contents of address
16
FFFE7
is FF
16
16
ecution starts from the address
shown by the vector in the
relocatable vector table.
16
16
16
16
16
16
are reserved bits. Set them to "1111
LSB
0 0 0 0
to FFFFF
. Table 9.1 lists the
16
16
Reference
M16C/60, M16C/20
serise software
maual
, program ex-
Address match interrupt
Watchdog timer
Clock generating circuit
Voltage detection circuit
_______
NMI interrupt
Reset
".
2
9. Interrupts
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