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M16C/62P Group (M16C/62P, M16C/62PT)
12.4 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 12.2 shows the interrupt vector.
Figure 12.2 Interrupt Vector
12.4.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 12.1 lists the fixed
vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors
are used by the ID code check function. For details, refer to the 22.2 Flash Memory Rewrite Disabling
Function.
Table 12.1 Fixed Vector Tables
Interrupt Source
Undefined Instruction (UND instruction)
Overflow (INTO instruction)
(2)
BRK Instruction
Address Match
(1)
Single Step
Watchdog Timer,
Oscillation Stop and, Re-Oscillation Detection,
Voltage Down Detection
________
(1)
DBC
_______
NMI
Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the
vector in the relocatable vector table.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Vector address (L)
Vector address (H)
f o
3
6
4
page 92
MSB
Low-order address
Middle-order address
High-order
0 0 0 0
0 0 0 0
Vector Table Addresses
Address (L) to address (H)
FFFDCh to FFFDFh
FFFE0h to FFFE3h
FFFE4h to FFFE7h
FFFE8h to FFFEBh
FFFECh to FFFEFh
FFFF0h to FFFF3h
FFFF4h to FFFF7h
FFFF8h to FFFFBh
FFFFCh to FFFFFh
LSB
address
0 0 0 0
Reference
M16C/60, M16C/20 Series
software manual
12.9 Address Match Interrupt
13. Watchdog Timer,
10. Clock Generating Circuit,
6. Voltage Detection Circuit
_______
12.7 NMI Interrupt
5. Reset
12. Interrupt
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