Interrupts And Interrupt Vector - Renesas M16C Series Hardware Manual

R8C/11 Group

10.1.4 Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respec-
tive interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in
the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.
Figure 10.2 Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from 0FFDC
the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of
fixed vectors are used by the ID code check function. For details, refer to Section 17.3, "Functions to
Prevent Flash Memory from Rewriting."
Table 10.1 Fixed Vector Tables
Interrupt factor
Undefined instruction 0FFDC
Overflow
BRK instruction
Address match
(1)
Single step
• Watchdog timer
• Oscillation stop
detection
• Voltage detection
(Reserved)
(Reserved)
Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development sup-
port tools.
Rev.1.20 Jan 27, 2006
REJ09B0062-0120
MSB
Vector address (L)
Vector address (H)
Vector addresses
Address (L) to address (H)
to 0FFDF
16 16
0FFE0 to 0FFE3
16 16
0FFE4 to 0FFE7
16 16
0FFE8 to 0FFEB
16 16
0FFEC to 0FFEF
16 16
0FFF0 to 0FFF3
16 16
0FFF4 to 0FFF7
16 16
0FFF8 to 0FFFB
16 16
0FFFC to 0FFFF
16 16
page 50 of 204
Low address
Mid address
0 0 0 0 High address
0 0 0 0 0 0 0 0
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the contents of address
0FFE7 is FF , program ex-
16 16
ecution starts from the address
shown by the vector in the
relocatable vector table.
10.1 Interrupt Overview
LSB
to 0FFFF . Table 10.1 lists
16 16
Reference
R8C/Tiny series
software manual
18.1 Address match
interrupt
11. Watchdog timer
6. Clock generation
circuit
5.4 Voltage detection
circuit
5. Reset