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M16C/62P Group (M16C/62P, M16C/62PT)
12.4
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt
vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt
vector. Figure 12.2 shows the Interrupt Vector.
Figure 12.2
Interrupt Vector
12.4.1
Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 12.1 lists the Fixed
Vector Tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are used
by the ID code check function. For details, refer to the 22.2 Functions To Prevent Flash Memory from
Rewriting.
Table 12.1
Fixed Vector Tables
Interrupt Source
Undefined Instruction (UND instruction)
Overflow (INTO instruction)
(2)
BRK Instruction
Address Match
(1)
Single Step
Watchdog Timer,
Oscillation Stop and Re-Oscillation
Detection,
Low Voltage Detection
(1)
DBC
NMI
Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the
vector in the relocatable vector table.
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Vector address (L)
Vector address (H)
Page 109 of 390
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MSB
Low-order address
Middle-order address
0 0 0 0
0 0 0 0
Vector Table Addresses
Address (L) to Address (H)
FFFDCh to FFFDFh
FFFE0h to FFFE3h
FFFE4h to FFFE7h
FFFE8h to FFFEBh
FFFECh to FFFEFh
FFFF0h to FFFF3h
FFFF4h to FFFF7h
FFFF8h to FFFFBh
FFFFCh to FFFFFh
LSB
High-order
address
0 0 0 0
Reference
M16C/60, M16C/20 Series
software manual
12.9 Address Match Interrupt
13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
12.7 NMI interrupt
5. Reset
010-62245566 13810019655
12. Interrupt
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