Central Processing Unit (Cpu) - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The register bank is comprised of 7 registers (R0, R1, R2, R3, A0, A1
and FB) out of 13 CPU registers. Two sets of register banks are provided.
b31
NOTES:
1. The register bank is comprised of these registers. Two sets of register banks are provided.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0, R1, R2 and R3 registers are 16 bit registers for transfer and arithmetic/logic operations.
The R0 and R1 registers can be split into high-order bits(R0H, R1H) and low-order bits (R0L, R1L) to be
used seperately as 8-bit data registers. Conversely, R2 and R0 can be combined with R2 to be used as a
32-bit data register (R2R0). The same applies to R1 and R2.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register
relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
b15
R2
R0H(R0's high bits)
R3
R1H(R1's high bits)
b19
b15
INTBH
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b15
b15
b15 b8
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f o 3 8 5
b8 b7 b0
R0L(R0's low bits)
R1L(R1's low bits)
R2
R3
A0
A1
FB
b0
INTBL
Interrupt table register
b0
PC
Program counter
b0
US P
User stack pointer
IS P
Interrupt stack pointer
SB
Static base register
b0
FL G
Flag register
b b7 b0
2. Central Processing Unit(CPU)
(1)
Data registers
(1)
Address registers
(1)
Frame base registers
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved space
Processor interrupt priority level
Reserved space