Chapter 2. Central Processing Unit (Cpu) - Renesas M16C Series Hardware Manual

R8C/11 Group
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
b 3 1
N O T E S :
1 . A r e g i s t e r b a n k c o m p r i s e s t h e s e r e g i s t e r s . T w o s e t s o f r e g i s t e r b a n k s a r e p r o v i d e d
Figure 2.1 CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
Rev.1.20 Jan 27, 2006
REJ09B0062-0120
b 1 5
R 2
R0H (high-order of R0)
R 3
R1H (high-order of R1) R1L (low-order of R1)
b 1 9
b 1 5
I N T B H
T h e 4 - h i g h o r d e r b i t s o f I N T B a r e I N T B H a n d
t h e 1 6 - l o w b i t s o f I N T B a r e I N T B L .
b19
b 1 5
b15
b 1 5 b 8
I P L
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b 8 b7 b 0
R0L (low-order of R0)
R2
R3
A0
A1
F B
b 0
I N T B L
b 0
PC
b 0
U S P
ISP
SB
b0
F L G
b7 b 0
U I O B S Z D C
2. Central Processing Unit (CPU)
D a t a r e g i s t e r s
( 1 )
A d d r e s s r e g i s t e r s
( 1 )
F r a m e b a s e r e g i s t e r s
( 1 )
I n t e r r u p t t a b l e r e g i s t e r
P r o g r a m c o u n t e r
U s e r s t a c k p o i n t e r
Interrupt stack pointer
Static base register
Flag register
Carry flag
D e b u g f l a g
Z e r o f l a g
Sign flag
Register bank select flag
O v e r f l o w f l a g
I n t e r r u p t e n a b l e f l a g
S t a c k p o i n t e r s e l e c t f l a g
R e s e r v e d b i t
Processor interrupt priority level
Reserved bit