Chapter 2. Central Processing Unit (Cpu) - Renesas M16C FAMILY Hardware Manual

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
Note 1: These registers comprise a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
Rev.0.91 2003 Sep 08
b15
R2
R0H(R0's high bits)
R3
R1H(R1's high bits) R1L(R1's low bits)
b19
b15
INTBH
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b15
b15
b15 b8
IPL
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b8 b7 b0
R0L(R0's low bits)
R2
R3
A0
A1
FB
b0
INTBL
b0
PC
b0
USP
ISP
SB
b0
FLG
b7 b0
U I O B S Z D C
2. Central Processing Unit (CPU)
Data registers (Note 1)
Address registers (Note 1)
Frame base registers (Note 1)
Interrupt table register
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area