21.4.3 Control Signal Timing
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Control signal timing is shown as follows:
•
Reset input timing
Figure 21-18 shows the reset input timing.
•
Reset output timing
Figure 21-19 shows the reset output timing.
•
Interrupt input timing
Figure 21-20 shows the input timing for NMI and IRQ
•
Bus-release mode timing
Figure 21-21 shows the bus-release mode timing.
ø
RES
MD2 to MD0
ø
RESO
t
RESS
t
MDS
Figure 21-18 Reset Input Timing
t
RESD
Figure 21-19 Reset Output Timing
701
to IRQ
.
5
0
t
RESS
t
RESW
t
RESD
t
RESOW