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Contention between Buffer Register Write and Input Capture: If a buffer register is used for
input capture buffering and an input capture signal occurs in the T
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capture takes priority and the write to the buffer register is not performed.
See figure 10-69.
ø
Address bus
Internal write signal
Input capture signal
GR
BR
Figure 10-69 Contention between Buffer Register Write and Input Capture
Buffer register write cycle
T
T
T
1
2
3
BR address
N
M
388
state of a write cycle, input
3
X
TCNT value
N
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