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14.2.3 Serial Mode Register (SMR)
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Bit 7 of SMR has a different function in smart card interface mode. The related serial control
register (SCR) changes from bit 1 to bit 0. However, this function does not exist in the flash
memory version.
Bit
GM
Initial value
Read/Write
R/W
Bit 7-GSM Mode (GM): Set at 0 when using the regular smart card interface. In GSM mode, set
to 1. When transmission is complete, initially the TEND flag set timing appears followed by clock
output restriction mode. Clock output restriction mode comprises serial control register bit 1 and
bit 0.
Bit 7
GM
Description
0
Using the regular smart card interface mode
• The TEND flag is set 12.5 etu after the beginning of the start bit
• Clock output on/off control only
1
Using the GSM mode smart card interface mode
• The TEND flag is set 11.0 etu after the beginning of the start bit
• Clock output on/off and fixed-high/fixed-low control
Bits 6 to 0—Operate in the same way as for the normal SCI.
For details, see section 13.2.5, Serial Mode Register (SMR).
7
6
5
CHR
PR
0
0
0
R/W
R/W
4
3
2
O/E
STOP
MP
0
0
0
R/W
R/W
R/W
503
1
0
CKS1
CKS0
0
0
R/W
R/W
(Initial value)
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