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Address bus
CS
n
AS
RD
Read
D
to D
15
8
access
D to D
7
0
HWR
LWR
Write
access
D
to D
15
8
D to D
7
0
Note: n = 7 to 0
Figure 6-7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
Bus cycle
T
1
Odd external address in area n
High
Undetermined data
(Byte Access to Odd Address)
128
T
T
2
3
Invalid
Valid
Valid
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