Serial Status Register (Ssr) - Hitachi H8/3048 Hardware Manual

Bit 2—Smart Card Data Inverter (SINV): Inverts data logic levels. This function is used in
combination with bit 3 to communicate with inverse-convention cards. SINV does not affect the
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logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings.
Bit 2
SINV Description
0 Unmodified TDR contents are transmitted
Received data is stored unmodified in RDR
1 Inverted TDR contents are transmitted
Received data is inverted before storage in RDR
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0
SMIF Description
0 Smart card interface function is disabled
1 Smart card interface function is enabled

14.2.2 Serial Status Register (SSR)

The function of SSR bit 4 is modified in the smart card interface. This change also causes a
modification to the setting conditions for bit 2 (TEND).
Bit 7
TDRE
Initial value 1
Read/Write R/(W)*
Note: * Only 0 can be written, to clear the flag.
6 5 4
RDRF ORER ERS
0
0 0
R/(W)* R/(W)* R/(W)*
Error signal status (ERS)
Status flag indicating that an
error signal has been received
501
3 2 1
PER TEND MPB
0 1 0
R/(W)* R R
Transmit end
Status flag indicating
end of transmission
(Initial value)
(Initial value)
0
MPBT
0
R/W