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Table D-1 Port States (cont)
www.DataSheet4U.com
Pin
Name
Mode
P5
to P5
1 to 4
3
0
5, 6
7
P6
1 to 6
0
7
P6
1 to 6
1
7
P6
1 to 6
2
7
P6
to P6
1 to 6
6
3
7
P7
to P7
1 to 7
7
0
P8
1 to 6
0
7
Legend
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
Note: * The bus cannot be released in mode 7.
Hardware Software
Standby
Reset
Mode
L
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
3
H*
T
T
T
T
T
T
T
T
T
850
Bus-
Standby
Released
Mode
Mode
T
T
keep
T
T
T
keep
—
keep
keep
keep
—
keep
T
(BRLE = 0)
T
(BRLE = 1)
keep
—
keep
L
(BRLE = 0)
H
(BRLE = 1)
keep
—
T
T
keep
—
T
T*
keep
keep
(RFSHE = 0) (RFSHE = 0) (RFSHE = 0)
RFSH
H
(RFSHE = 1) (RFSHE = 1) (RFSHE = 1)
keep
—
Program
Execution,
Sleep Mode
A
to A
19
16
Input port
(DDR = 0)
A
to A
19
16
(DDR = 1)
I/O port
I/O port
WAIT
I/O port
I/O port
BREQ
I/O port
I/O port
(BRLE = 0)
or BACK
(BRLE = 1)
I/O port
AS, RD,
HWR, LWR
I/O port
Input port
I/O port
or RFSH
I/O port
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