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Table 1-3 Pin Functions (cont)
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Type
Symbol
RFSH
Refresh
controller
CS
3
RD
HWR
LWR
DMA
DREQ
1
controller
DREQ
0
(DMAC)
TEND
,
1
TEND
0
16-bit
TCLKD to
integrated
TCLKA
timer unit
TIOCA
4
(ITU)
TIOCA
0
TIOCB
4
TIOCB
0
TOCXA
TOCXB
Pin No.
I/O
87
Output Refresh: Indicates a refresh cycle
Output Row address strobe RAS: Row address
88
Output Column address strobe CAS: Column
70
Output Upper write UW: Write enable signal for
71
Output Lower write LW: Write enable signal for DRAM
72
,
9, 8
Input
94, 93
Output Transfer end 1 and 0: These signals indicate
96 to 93
Input
to
4, 2, 99,
Input/
97, 95
output
to
5, 3, 100,
Input/
98, 96
output
6
Output Output compare XA4: PWM output
4
7
Output Output compare XB4: PWM output
4
12
Name and Function
strobe signal for DRAM connected to area 3
address strobe signal for DRAM connected to
area 3; used with 2WE DRAM.
Write enable WE: Write enable signal for
DRAM connected to area 3; used with 2CAS
DRAM.
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS DRAM.
connected to area 3; used with 2WE DRAM.
Lower column address strobe LCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS DRAM.
DMA request 1 and 0: DMAC activation
requests
that the DMAC has ended a data transfer
Clock input D to A: External clock inputs
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
Input capture/output compare B4 to B0:
GRB4 to GRB0 output compare or input
capture, or PWM output
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