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18.7.6 Erasing Flowchart and Sample Program
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Flowchart for Erasing One Block
No
Address + 1 → address
Start
Write 0 data in all addresses
to be erased (prewrite)
*1
n = 1
Set
V
E
bit
PP
(
bit = 1 in FLMCR)
V
E
PP
Wait (z) µs
Set erase block register
(set bit of block to be erased to 1)
Set top address in block
as verify address
Wait initial value setting x = 6.25 ms
Enable watchdog timer
*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms
Clear E bit
Disable watchdog timer
Select erase-verify mode
(EV bit = 1)
) µs
Wait (t
VS1
*3
Dummy write to verify address
(flash memory latches address)
) µs
Wait (t
VS2
*4
Verify (read memory)
OK
Last address?
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
Clear
V
E
bit
PP
End of block erase
Figure 18-16 Erasing Flowchart
Notes: 1. Program all addresses to be
erased by following the prewrite
flowchart.
2. Set the watchdog timer overflow
interval to the value indicated in
table 18-15.
3. For the erase-verify dummy
write, write H'FF using a byte
transfer instruction.
4. Read to verify data from the
memory using a byte transfer
instruction.
5. t
: 4 µs
VS1
z:
5 to 10 µs
t
: 2 µs
VS2
N:
602
6. The erase time x is successively
incremented by the initial set
value × 2
initial value of 6.25 ms or less
should be set, and the time for
one erasure should be 50 ms or
Erasing ends
less.
No good
Clear EV bit
Erase-verify ends
No
n ≥ N?
Yes
Clear erase block register
(clear bit of block to be
erased to 0)
Clear
V
E
bit
PP
Erase error
595
n–1
(n = 1, 2, 3, 4). An
→ n
n + 1
Yes
n ≥ 5?
No
Double the erase time
(x × 2 → x)
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