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18.4.5 Input/Output Pins
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Flash memory is controlled by the pins listed in table 18-9.
Table 18-9 Flash Memory Pins
Pin Name
Programming power
Mode 2
Mode 1
Mode 0
Transmit data
Receive data
The transmit data and receive data pins are used in boot mode.
18.4.6 Register Configuration
The flash memory is controlled by the registers listed in table 18-10.
Table 18-10 Flash Memory Registers
Address
Name
H'FF40
Flash memory control
register
H'FF42
Erase block register 1
H'FF43
Erase block register 2
H'FF48
RAM control register
Notes: 1. The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled).
2. In modes 1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be
modified and is always read as H'FF.
Abbreviation
Input/Output
V
Power supply
PP
MD
Input
2
MD
Input
1
MD
Input
0
TXD
Output
1
RXD
Input
1
Abbreviation
FLMCR
EBR1
EBR2
RAMCR
573
Function
Apply 12.0 V
H8/3048F operating mode
programming
H8/3048F operating mode
programming
H8/3048F operating mode
programming
Serial transmit data output
Serial receive data input
R/W
Initial Value
*2
*1
R/W
H'00
*2
*1
R/W
H'00
*2
*1
R/W
H'00
R/W
H'70
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