Hitachi H8/3048 Hardware Manual page 703

Single-chip microcomputer
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ø
A
to A
23
0
AS
RD (read)
D
to D
15
0
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
WAIT
Figure 21-9 Basic Bus Cycle: Three-State Access with One Wait State
T
T
1
2
t
t
WTS
WTH
695
T
W
t
t
WTS
WTH
T
3

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