Hitachi H8/3048 Hardware Manual page 790

TOCR—Timer Output Control Register
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Bit
Initial value
Read/Write
External trigger disable
0 Input capture A in channel 1 is used as an external trigger signal in
1 External triggering is disabled
Note: * When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling ITU
output.
7 6 5
—
— —
1 1 1
— — —
Output level select 3
0 TIOCB , TOCXA , and TOCXB outputs are inverted
3
1 TIOCB , TOCXA , and TOCXB outputs are not inverted
3
Output level select 4
0 TIOCA , TIOCA , and TIOCB outputs are inverted
3 4
1 TIOCA , TIOCA , and TIOCB outputs are not inverted
3 4
reset-synchronized PWM mode and complementary PWM mode
H'91
4 3 2
XTGD
— —
1 1 1
R/W — —
4 4
4 4
4
4
783
ITU (all channels)
1 0
OLS4 OLS3
1 1
R/W R/W
*