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Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh
during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set
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to 1, pseudo-static RAM can be self-refreshed when the H8/3048 Series enters software standby
mode. When PSRAME = 0 and DRAME = 1, after the SRFMD bit is set to 1, DRAM can be self-
refreshed when the H8/3048 Series enters software standby mode. In either case, the normal
access state resumes on exit from software standby mode.
Bit 7
SRFMD Description
0
DRAM or PSRAM self-refresh is disabled in software standby mode
1
DRAM or PSRAM self-refresh is enabled in software standby mode
Bit 6—PSRAM Enable (PSRAME) and Bit 5—DRAM Enable (DRAME): These bits enable
or disable connection of pseudo-static RAM and DRAM to area 3 of the external address space.
When DRAM or pseudo-static RAM is connected, the bus cycle and refresh cycle of area 3
consist of three states, regardless of the setting in the access state control register (ASTCR). If
AST3 = 0 in ASTCR, wait states cannot be inserted.
When the PSRAME or DRAME bit is set to 1, bits 0, 2, 3, and 4 in RFSHCR and registers
RTMCSR, RTCNT, and RTCOR are write-disabled, except that the CMF flag in RTMCSR can be
cleared by writing 0.
Bit 6
Bit 5
PSRAME
DRAME
0
0
1
1
0
1
Description
Can be used as an interval timer
(DRAM and PSRAM cannot be directly connected)
DRAM can be directly connected
PSRAM can be directly connected
Illegal setting
151
(Initial value)
(Initial value)
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