Hitachi H8/3048 Hardware Manual page 678

Table 21-7 Timing of On-Chip Supporting Modules
www.DataSheet4U.com
Condition A: V = 2.7 V to 5.5 V, AV
CC
V = AV
SS
specifications), T
Condition B: V = 3.15 V to 5.5 V, AV
CC
V = AV
SS
specifications), T
Condition C: V = 5.0 V ± 10%, AV
CC
V = AV
SS
specifications), T
Item Symbol Min
DMAC DREQ setup
t
DRQS
time
DREQ hold
t
DRQH
time
TEND delay
t
TED1
time 1
TEND delay
t
TED2
time 2
ITU Timer output t
TOCD
delay time
Timer input t
TICS
setup time
Timer clock t
TCKS
input setup time
Timer Single t
TCKWH
clock
edge
pulse
Both t
TCKWL
width
edges
SCI Input Asyn- t
SCYC
clock chronous
cycle
Syn- t
SCYC
chronous
Input clock rise t
SCKr
time
Input clock fall t
SCKf
time
Input clock t
SCKW
pulse width
= 2.7 V to 5.5 V, V
CC
= 0 V, ø = 1 MHz to 8 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
= 3.15 V to 5.5 V, V
CC
= 0 V, ø = 1 MHz to 13 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
= 5.0 V ± 10%, V
CC
= 0 V, ø = 1 MHz to 18 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
Condition A Condition B
8 MHz 13 MHz
Max Min
40 — 40
10 — 10
— 100 —
— 100 —
— 100 —
50 — 50
50 — 50
1.5 — 1.5
2.5 — 2.5
4 — 4
6 — 6
— 1.5 —
— 1.5 —
0.4 0.6 0.4
670
= 2.7 V to AV
REF
= –20°C to +75°C (regular
a
= 3.15 V to AV
REF
= –20°C to +75°C (regular
a
= 4.5 V to AV
REF
= –20°C to +75°C (regular
a
Condition C
16 MHz 18 MHz
Max Min Max Min
— 30 — 30
— 10 — 10
100 — 50 —
100 — 50 —
100 — 100 —
— 50 — 50
— 50 — 50
— 1.5 — 1.5
— 2.5 — 2.5
— 4 — 4
— 6 — 6
1.5 — 1.5 —
1.5 — 1.5 —
0.6 0.4 0.6 0.4
,
CC
,
CC
,
CC
Test
Conditions
Max Unit
— ns Figure 21-30
—
50 Figure 21-28,
Figure 21-29
50
100 ns Figure 21-24
—
— Figure 21-25
— t
CYC
—
— t Figure 21-26
CYC
—
1.5
1.5
0.6 t
SCYC