Hitachi H8/3048 Hardware Manual page 342

Single-chip microcomputer
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Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
OVF flag in TSR when OVF is set to 1.
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Bit 2
OVIE
Description
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Bit 1
IMIEB
Description
0
IMIB interrupt requested by IMFB is disabled
1
IMIB interrupt requested by IMFB is enabled
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
Bit 0
IMIEA
Description
0
IMIA interrupt requested by IMFA is disabled
1
IMIA interrupt requested by IMFA is enabled
330
(Initial value)
(Initial value)
(Initial value)

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