Hitachi H8/3048 Hardware Manual page 12

15.3 CPU Interface ................................................................................................................. 532
15.4 Operation ........................................................................................................................ 533
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15.4.1 Single Mode (SCAN = 0) ............................................................................... 533
15.4.2 Scan Mode (SCAN = 1).................................................................................. 535
15.4.3 Input Sampling and A/D Conversion Time .................................................... 537
15.4.4 External Trigger Input Timing........................................................................ 538
15.5 Interrupts......................................................................................................................... 539
15.6 Usage Notes .................................................................................................................... 539
Section 16 D/A Converter
16.1 Overview......................................................................................................................... 545
16.1.1 Features........................................................................................................... 545
16.1.2 Block Diagram................................................................................................ 545
16.1.3 Input/Output Pins............................................................................................ 546
16.1.4 Register Configuration.................................................................................... 546
16.2 Register Descriptions...................................................................................................... 547
16.2.1 D/A Data Registers 0 and 1 (DADR0/1) ........................................................ 547
16.2.2 D/A Control Register (DACR) ....................................................................... 547
16.2.3 D/A Standby Control Register (DASTCR)..................................................... 549
16.3 Operation ........................................................................................................................ 550
16.4 D/A Output Control ........................................................................................................ 551
16.5 Usage Notes .................................................................................................................... 551
Section 17 RAM
17.1 Overview......................................................................................................................... 553
17.1.1 Block Diagram................................................................................................ 553
17.1.2 Register Configuration.................................................................................... 554
17.2 System Control Register (SYSCR)................................................................................. 555
17.3 Operation ........................................................................................................................ 556
Section 18 ROM
18.1 Overview......................................................................................................................... 557
18.1.1 Block Diagram................................................................................................ 558
18.2 PROM Mode................................................................................................................... 559
18.2.1 PROM Mode Setting ...................................................................................... 559
18.2.2 Socket Adapter and Memory Map.................................................................. 559
18.3 PROM Programming ...................................................................................................... 562
18.3.1 Programming and Verification........................................................................ 562
18.3.2 Programming Precautions............................................................................... 567
18.3.3 Reliability of Programmed Data..................................................................... 568
18.4 Flash Memory Overview ................................................................................................ 569
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