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TCNT—Timer Counter
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Bit
7
Initial value
0
Read/Write
R/W
RSTCSR—Reset Control/Status Register
Bit
7
WRST
Initial value
0
Read/Write
R/(W)
*
Watchdog timer reset
0 [Clearing condition]
• Reset signal input at RES pin
• When WRST= "1", write "0" after reading WRST flag
1 [Setting condition]
TCNT overflow generates a reset signal
Note:
Only 0 can be written in bit 7, to clear the flag.
*
6
5
4
0
0
0
R/W
R/W
R/W
Count value
6
5
4
RSTOE
—
—
0
1
1
R/W
—
—
Reset output enable
0 External output of reset signal is disabled
1 External output of reset signal is enabled
792
H'A9 (read),
H'A8 (write)
3
2
1
0
0
0
R/W
R/W
R/W
H'AB (read),
H'AA (write)
3
2
1
—
—
—
1
1
1
—
—
—
WDT
0
0
R/W
WDT
0
—
1
—
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